At the time of the LPC55S6x launch, the latest silicon revision of the LPC55S6x is revision 1B. Since Nov,2019, all the LPCXpresso55S69 EVK boards marked as Revision A2 are equipped with revision 1B silicon.
NXP introduced its new debug session request functionality on silicon revision 1B. For some IDE versions, the method of initiating a debug session is designed for current 1B silicon revisions and will result in an endless loop when used on older revision 0A parts. The protocol for this debug connection method is included in the latest LPC55S6x/S2x/2x User Manual, section Debug session protocol.
- MCUXpresso IDE:
Due to above debug access protocol changes, the latest MCUXpresso IDE v11.0.1, who expects silicon to handle silicon revision 1B debug session requests correctly, can’t connect silicon revision 0A production under some situations. When connecting LPCXpresso55S69 Revision A1 board, you may have connection error like this:
NXP has released MCUXpresso IDE v11.0.1 LPC55xx Debug Hotfix1 for this issue. Please follow the steps to fix the issue if you use IDE v11.0.1 with silicon revision 0A:
The newer version of MCUXpresso IDE has already fixed this issue.
According to our test:
IAR Embedded Workbench for ARM v8.42 and later can support both silicon revision 1B and 0A production without issue, which can be downloaded from
Note: The IAR 8.50.5 changed the CMSIS-DAP debug support for trustzone feature. There is known debug issue with the combination of IAR 8.50.5+SDK2.8.0. Thus our recommendation is:
- Use IAR 8.50.5 with SDK2.8.0
- Use IAR 8.40.2 with SDK 2.7.1
- Keil MDK:
Both Keil MDK v5.28 and v5.29+ latest LPC55S69 pack v12.01 can support silicon reversion 1B without problem but can’t support silicon revision 0A.
LPC55S69 Revision 0A vs. 1B
Add New Debug Session Access Method
Secure Boot Revision
Maximum CPU Frequency
IDE revision required
1. MCUXpresso IDE v11.0.0 and older
2. MCUXpresso IDE v11.0.1 + hotfix1
3. MCUXpresso IDE next version
MCUXpresso IDE v11.0.0 and newer
SDK2.5 and newer are supported; SDK2.6.3 and newer are recommended
SDK2.6.3 and newer
LPC55S69 Defect Fix: 0A vs. 1B
Defect: For PRINCE encrypted region, partial erase cannot be performed
Defect: For PUF based key provisioning, a reset must be performed
Defect: Unprotected sub regions in PRINCE defined regions cannot be used.
Defect: Last page of image is erased when simultaneously programming the signed image and CFPA region
Defect: the minimum operating range is 1.85 V.
Fixed: The LPC55S6x operating voltage range specification is from 1.80 V to 3.6 V.
Defect: PHY does not auto-power down in suspend mode
For more detail, see Errata sheet LPC55S6x which can be downloaded from NXP web site.
Note that NO BOARDS WERE EVER SOLD THROUGH DISTRIBUTION WITH PRE-PRODUCTION SILICON. In case you have board marked with Revision 1, 2 ,A, or A1 board with 1B silicon, contact NXP to ask for production replacement.
Get Silicon Revision:
The silicon revision info is marked on the chip and board revision is marked on the board silkscreen. For silicon revision marking information, please consult LPC55S6x Data Sheet section 4. Marking . Below is an example of silicon revision marking information where revision is highlighted in red:
The user application can also get the silicon revision through chip revision ID and number: SYSCON->DIEID: