Enable i.MX8MM DDR3L DVFS and Retention function driver

Document created by Hongting Dong Employee on Jul 15, 2019
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Some customers want to use the retention and DVFS(dynamic voltage and frequency scaling) functions like lpddr4 and ddr4 on the i.MX8MM DDR3L platform.

I hope this article can help you.


Software:Linux 4.14.98_2.0.0_ga

Hardware:NXP i.MX8MM DDR3L Validation Board(VBD)


The patch file is currently validated only on the NXP i.MX8MM DDR3L validation board and is for reference only.


Generate a new script

  1. Create DDR stress test script using DDR3L RPA (Currently the DDR3L RPA tool is only available for 800MHz, you can modify a suitable script according to the NXP DDR3L VBD script).
  2. Open the DDR stress test on the DDR3L board and select the script from the previous step.
  3. Connect to the appropriate UART comm port.
  4. Hit Download.
  5. Upon successful Download, run calibration (hit Calibration button).
  6. Under “Format”, use the pull down menu to select “ARRAY”.
  7. Hit Gen Code (this will generate the DDR3L driver code in the new array format, which is a single C file titled “ddr3l_timing.c”.



Currently, the stress test generates an error within the file. In the default ddr3l_timing.c file generated from NXP’s DDR3L validation board, there is an error you can be seen like:


{ 0xd0000, 0x1 },



These two lines of code are repeats of the previous two lines and will result in a compile error.  Simply remove these two lines to correct it.


Because there is only 1D training when device is DDR3L, you need to do1600MTS training after 100MTS training

It means that which ends with 1600MTS parameter in ddr_dram_fsp_msg in the ddr3l_timing.c file.


Build flash.bin file for DDR3L

DDR4 and LPDDR4 currently have a framework but do not support DDR3L.

The attached patch applies the necessary files to support the DDR3L framework.

This patch includes an updated framework to support the new array format for DDR configuration.

The patch file contains modifications to the u-boot and arm trust firmware source code.

Once the patch is applied, it is populates these various new files to support DDR3L.

One file is the ddr3l_timing.c that was generated from the NXP DDR3L validation board.  You will need to replace this file with your customer ddr3l_timing.c file in board/freescale/imx8mm_val/


Build Image file and dtb file

Because the tested platform is NXP DDR3L VBD, the dtb file fsl-imx8mm-ddr3l-val.dtb will be used.

The default dtb disables the busfreq function. You need to open it.

This part of the modification needs to be modified according to your customer's board.

busfreq {
-               status = "disabled";
+               status = "okay";


For more details, please view the patch to see what changes take place.