NXP’s new 65 V LDMOS technology: designed for ease of use

Document created by edk Employee on May 30, 2017Last modified by edk Employee on Sep 14, 2017
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1. More power – Higher voltage enables higher power density, which helps reduce the number of transistors to combine.
2. Faster development time – With higher voltage, the output power can be increased while retaining a reasonable output impedance.
3. Design Reuse – This impedance benefit also ensures pin-compatibility with current 50 V LDMOS transistors for better scalability.
4. Manageable current level – Higher voltage reduces the current losses in the system.
5. Wide safety margin – The higher breakdown voltage of 182 V improves ruggedness and allows for higher efficiency classes of operation






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