QE TDM Working with QUICC Multi-channel Controller

Document created by Yiping Wang Employee on Nov 7, 2016
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Time division multiplexing(TDM) is a communication term for multiplexing several channels on the same link. QUICC multi-channel controller(QMC) is a firmware package which uses a unified communication controller(UCC) working in slow mode. The QMC is used to emulates up to 64 time-division serial channels through a time-division-multiplexed(TDM) physical interface. Each of QMC channels can be independently programmed to support either HDLC or transparent protocols. This document introduces TDM QMC driver implementation in Linux Kernel for the processors with QE UCC working in slow mode.

 

Data flow over a QMC channel involves a TDM line and a UCC, working in slow mode. For each channel, Tx data flow consists of data transfer from the external memory to the TDM physical connection. Rx data flow consists of data transfer from the TDM physical connection to the external memory. In both data flows, the major stations are: data buffers, UCC, and the TDM line. Please refer to the following figure for the data flow, the driver requires to configure two levels of routing tables. The first level consists of the SI RAM routing tables, Tx and Rx, which are common to other controllers as well.

1. QE TDM QMC Driver Introduction

 

2. Driver Architecture and Components

2.1 QMC Driver Memory Allocation

 

2.2 QMC and TDM Devices Initialization

2.2.1 SI RAM entry initialization

2.2.2 UCC Slow Mode QMC Initialization

2.2.3 QMC Channel Initialization

2.2.4 QMC TSA Slot Initialization

 

2.3 QMC Channel Interrupt Handling

 

2.4 QMC and TDM Configuration

2.4.1 Enable and Configure QMC Channel

2.4.2 Enable QMC

2.4.3 Enable TDM

 

3. QMC TDM Driver Calling Sequence

4. QMC TDM DTS Definition

5. Configure QMC TDM Driver and Running the Testing Program

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