This demonstrator gives a first impression on the future 5G technologies used to increase bandwidth and throughput. One of these technologies is millimetre wave and the use of “pencil” beams, along with large bandwidth requirements. NXP shows the future of 5G architecture and how a smart split of the baseband processing can leverage high throughput, yet maintaining a small latency. NXP proposes a split architecture processing between a "traditional", yet powerful multicore scalar DSP + accelerator + network processor and a vector DSP architecture.
We show an end-to-end demo, consisting of a B4860QDS and D4400RDB, based on AFD4400, for the transmitter and a mirrored setup for receiver.
- B4860QDS board, containing B4860 High-end Qonvergence QorIQ product performing user processing, on MAPLE Layer-1 accelerator and on StarCore 3900 DSP.
- AFD4400RDB board, containing AFD4400 product performing antenna processing on the VSPA vector signal processor.
- Software tools to program the required chipsets.
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