Configure, Validate, and Optimize QorIQ with QCVS

Document created by Diana Torres Employee on May 6, 2016Last modified by Diana Torres Employee on Apr 18, 2017
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Demo

  • How to configure, validate and optimize DDR controller configuration for a QorIQ LS2080A device
  • How to validate the SerDes controller lanes [configured in digital loopback mode] configurations for a QorIQ LS2085A device
  • How to generate a PBL binary ready to be flashed to target for a QorIQ LS device

 

 

 

 

Features:

  • Configuration and validation of SoC elements [DDR, SerDes, PBL] from QorIQ LS devices with a few mouse clicks

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Featured NXP Products:

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