This section explains the LPC32x0 boot process for the various non-volatile memory types or the UART.
Depending on the boot device, there may be limitations to the boot image size. This limitation may prevent a desired image from initially loading and executing – instead requiring a smaller boot loader to be loaded first and then using it to load and run a more capable boot loader or application.
LPC32x0 boot options
The LPC32x0 supports booting from small and large block NAND FLASH, SPI EEPROMS or FLASH, NOR FLASH, and via the UART. In production systems, the UART boot method isn't used. However, the UART boot method serves a useful purpose in early board debug,
The boot order for the LPC32x0 is as follows: UART, SPI, NOR, NAND. UART boot can be disabled to reduce boot time. Each boot device will be tried prior to the next device. A device is bootable if the boot ROM locates a special boot pattern that identifies the device as bootable. It's possible that a system can have SPI FLASH, NOR FLASH, and NAND FLASH and only boot from NAND FLASH although the SPI and NOR methods are attempted first. (For example, the Phytec 3250 board has all 3 of these boot devices, but normally boots from NAND FLASH).
When the LPC32x0 chip is reset, the internal boot ROM is executed. It queries each device looking for a special boot pattern used to identify the device as bootable. The first device that returns a correct pattern will be used by the boot ROM as the bootable device. The boot ROM will then either copy data from the bootable device (NAND and SPI FLASH) or transfer control to the bootable device (NOR FLASH).
Each boot method is explained in the following sections. See the LPC32x0 User's guide for more information on the LPC32x0 boot process.
The UART boot option allows a binary to be downloaded into the board and then executed prior to any code running in NAND, SPI, or NOR FLASH. This is useful for burning new images into FLASH, testing simple applications, or recovering the board from corrupt boot code.
UART boot is used with the burner tools in the CDL package to program the bootloader(s) into the boot device. UART5 is supported with the UART boot option, so new designs should make UART5 available for debugging. For a system that entirely runs from IRAM, this allows a system to download an image via the UART that provides interactive access once the image is executed. The downloaded interactive program can be used for bandwidth or memory tests, register dumps, further image loading, or other functions.
Initial versions of S1L can be used with this boot method to test different SDRAM configurations using the included SDRAM initialization code. Using this approach, startup and debug of the SDRAM code (one of the tougher issues of bringing up a new board) can be drastically simplified.
NOR FLASH boot
On a system that boots from NOR FLASH, the ARM core directly executes code from the NOR FLASH device starting at address 0xE0000004. The first 4 bytes at address 0xE0000000 are used for the special boot pattern value required by the boot ROM to identify the device as bootable and to provide the boot width (8, 16, or 32 bits).
SPI FLASH/EEPROM boot
On a system that boots from SPI, a small image is copied from the SPI EEPROM or FLASH device at offset 0x8 into IRAM at address 0x00000000. The first 4 bytes are used for the special boot pattern value required by the boot ROM. The next 4 bytes are used to designate the size of the image to load at offset 0x8 in the SPI device. After the image is loaded into IRAM, control is transferred to address 0x00000000.
The maximum image boot size that can be loaded with this method is 54K.
NAND FLASH boot
On a system that boots from NAND FLASH, a small image is copied from block 0 or block 1 of the NAND device into IRAM at address 0x00000000. The maximum bootable image size for NAND FLASH boot is 54K, or 1 block minus 1 page, whichever is smaller. The first page of the boot block is used to store boot information, such as the boot image size and values needed by the boot ROM used for the boot sequence.
For small block NAND (32 pages per block and 512 bytes per page) with the first page of the block dedicated to the boot ROM boot information, the maximum boot size is 31 pages of 512 bytes per page, or 15.5K. For large block NAND (64 pages of 2Kbytes per page), the maximum boot size is 54Kbytes.
The boot ROM always uses the MLC NAND controller for NAND boot. This requires the boot image booted from NAND by the boot ROM to be programmed into NAND with the MLC NAND controller or with the ECC algorithms required by the MLC NAND controller.