Using DMA transfer ADC result via SPI with TWR-KV10Z32 board

Document created by Hui_Ma Employee on Aug 14, 2015Last modified by Juan Padilla on Dec 13, 2017
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Kinetis KV10 chip is the entry point of the V Series product, which are designed for a wide range of BLDC, PMSM and ACIM motor control and digital power conversion applications. KV10 is using ARM Cortex-M0+ core, the core frequency could up to 75MHz. And KV10 provides various feature powerful modules, such as ADC modules (2x 16-bit ADCs with two capture and hold circuits and up to 1.2 MS/s samples rate in 12-bit mode — simultaneous measurement of current and voltage phase, reduced jitter on input values improving system accuracy 12-bit mode) and DMA modules (4-channel DMA — reduced CPU loading for improved application performance).

 

The demo is using PDB hardware trigger two ADC modules conversion (12-bit single-ended mode) at the same time; the two ADC modules will trigger each related DMA channels to transfer ADC result to ADC buffer located at SRAM (start from 0x2000_0000) when finish each conversion. The ADC DMA channel 0 will link to trigger DMA channel 2 to transfer ADC result from ADC result buffer to SPI FIFO. When DMA channel 2 transfer done, in related interrupt service routine will software trigger PDB to start the next round of ADC conversion.

Below is the processing chart:

flow chart.png

 

For the customer requires to transfer 9 ADC conversion results out (5 of ADC0 and 4 of ADC1) , the ADC buffer need interleaved storage result from two ADC modules. Below diagram shows the detailed info:

data range.png

 

Below is the test result and test environment. It will take almost 15.4us to get and transfer all 9 12-bit ADC conversion results.

DMA CH2 generate PDB trigger signal.png

test environment.png

 

The demo code is attached. The project is based on TWR-KV10Z32 Sample Code Package could be downloaded from here.

Wish it helps.

 

Original Attachment has been moved to: isr.h.zip
Original Attachment has been moved to: demo.c.zip

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