P1022/P1013 Hardware Specifications/Reference Manual Specific FAQs

Document created by Omar Cruz Lopez Employee on Aug 6, 2012Last modified by Omar Cruz Lopez Employee on Aug 6, 2012
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Can P1022 GPIO signals drive LEDs directly? What is the output current requirement (Iol / Ioh) for GPIO signals?

Yes, P1022 GPIO signals can drive LEDs directly. When GPIO is driven HIGH, to maintain a voltage of 2.4V, no more than 2mA should be drawn from the IO and conversely to maintain a 0.4V when GPIO is driven LOW no more than 2mA should be sunk into the IO.

Current limiting would have to be done through external resistors. Below are the current and voltage requirements:

@3.3V Input high voltage VIH 2V Input low voltage VIL 0.8V Input current (OVIN = 0 V or OVIN = OVDD) IIN — ±40 μA2 Output high voltage (OVDD = min, IOH = –2 mA) VOH 2.4V Output low voltage (OVDD = min, IOL = 2 mA) VOL 0.4V

@2.5V Input high voltage VIH 1.7V Input low voltage VIL 0.7V Input current (OVIN = 0 V or OVIN = OVDD) IIN — ±40 μA2 Output high voltage (OVDD = min, IOH = –2 mA) VOH 1.7V Output low voltage (OVDD = min, IOL = 2 mA) VOL 0.7V

@1.8V Input high voltage VIH 1.2V Input low voltage VIL 0.6V Input current (OVIN = 0 V or OVIN = OVDD) IIN — ±40 μA2 Output high voltage (OVDD = min, IOH = –0.5 mA) VOH 1.35V Output low voltage (OVDD = min, IOL = 0.5 mA) VOL 0.4V


Which registers are used to control the I/O states and data of GPIO1[], GPIO2[] and GPIO3[] signals when they are multiplexed as GPIO?

Below registers are used to control the I/O states and data of GPIO1[], GPIO2[] and GPIO3[] signals:

For GPIO1: Reg Correct Offset GPDIR : 0X000 GPODR : 0X004 GPDAT : 0X008 GPIER : 0X00C GPIMR : 0X010 GPICR : 0X014

For GPIO2: Reg Correct Offset GPDIR : 0X100 GPODR : 0X104 GPDAT : 0X108 GPIER : 0X10C GPIMR : 0X110 GPICR : 0X114

For GPIO3: Reg Correct Offset GPDIR : 0X200 GPODR : 0X204 GPDAT : 0X208 GPIER : 0X20C GPIMR : 0X210 GPICR : 0X214


P1022 Hardware Spec mentions that “USB1_STP pin must be set to the proper state during POR config”. Can you please elaborate on what could possibly be the proper setting for POR?

USB1_STP is a personality pin with as yet undefined function when it is 1'b0. Please ensure that this pin is not pulled low during POR for P1022 and P1013.


P1022EC revision F defines output delay time for eSDHC interface in table 52. Is there any specification regarding "output hold" time? If not, how should I consider about it?

The min value of Output delay time becomes the output hold. ( Half clock period - |min khov| ) becomes the input hold for the receiver chip.


How is the selection between eLBC and DIU signals done in P1022? Is it done through SPI signals? Why are SPI signals "-" in data phase of 16-bit GPCM?

Selection between eLBC and DIU signals is done via PMUXCR [eLBC_DIU], and INDEPENDENTLY selection between eSPI, eLBC or eSDHC signals is done via PMUXCR[SPI_eLBC].

Thus for SPI signals user only needs to use PMUXCR[SPI_eLBC]. And for 32-bit GPCM user has to set BOTH PMUXCR[eLBC_DIU] and PMUXCR[SPI_eLBC].


Using the TDM interface in shared mode (Tx clk and sync are used for Tx and Rx), are pullups / pulldowns required for TDM_RCK and TDM_RFS in P1022?

Actually the multiplexing happens at the SoC level and the selection of shared mode happens at the IP level, hence pins would not automatically revert to GPIO. It is recommended to be pulled to OVdd by 2k-10k.


Can you please describe the procedure for timer soft reset and reconfiguration for P1022?

Software must do the following before asserting TMR_CTRL[TMSR]: 1) Place the controller in graceful transmit stop (DMACTL[GTS]=1, wait for IEVENTGn[GTSC]=1) 2) Disable receive (MACCFG1[RX_EN]=0) Note: After setting timer soft reset (TMR_CTRL[TMSR]), software must leave the bit high for at least three 1588 reference clocks or tx_clk cycles, whichever is slower, before clearing the bit.


How should I handle 2 CKSTP_OUT signals for P1022? Note 11 on Table 1 in the P1013EC states that these need a weak pullup resistor. However, Table 4-13 in the P1022RM shows that these 2 signal default to 1 (as part of cfg_rom_loc). Do these pins need pullups?

The internal pull up for por_cfg pins is only for the duration when HRESET is asserted. So after POR pull up will be required. For handling this kind of a situation a tri state buffer with Enable tied to HRESET can be used. Add pull down at buffer input and pull up at buffer output.

While HRESET is asserted, the pull down is visible on the buffer output. After HRESET deassertion, buffer output is tri stated and pull up on the output of buffer pulls up the CKSTP_OUT signal.


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