P1021/P1012 Memory Controller/DDR Specific FAQs

Document created by Omar Cruz Lopez Employee on Aug 6, 2012
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Can you explain me the detailed description of bit functionality in field Error Capture ECC (ECE) for P1012/P1021?

Following is the correct description of bits in Error Capture ECC (ECE): 0:7 -8-bit ECC for the 16 bits in beats 0 & 4 in 16-bit bus mode; should be ignored for 32-bit and 64-bit mode 8:15 -8-bit ECC for the 16 bits in beats 1 & 5 in 16-bit bus mode; should be ignored for 32-bit and 64-bit bus mode 16:23 -8-bit ECC for the 16 bits in beats 2 & 6 in 16-bit bus mode; for the 32 bits in beats 0 & 2 & 4 & 6 in 32-bit bus mode; should be ignored for 64-bit mode 24:31 -8-bit ECC for the 16 bits in beats 3 & 7 in 16-bit bus mode; for the 32 bits in beats 1 & 3 & 5 & 7 in 32-bit bus mode; should be used for every beat in 64-bit mode Bits 0:15 bits are not reserved in P1012/P1021.


How can I support GPCM based Local Bus (like a boot NOR FLASH) on memory controller part with all 4 TDM ports in use due to pin mux restrictions in P1012/P1021?

You can boot from GPCM as the pins as configured as eLBC signals by default. But if you intent to use them simultaneously, you cannot. You'll have to use some isolation logic on board to switch from one protocol to other.


Is there a possibility to support higher density of DDR2/3 with P1021 at a later stage in design? For example JEDEC specifies 8Gbits density for DDR3.

Yes, there is a possibility to support higher density devices in P1021. For a single discrete memory (single chip select), the max memory size that can be supported is 4GB. With a single chip-select we can support max of 4 GB, so with two chip-select we can support a maximum of 8 GB with two discrete devices. HW spec.



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