Do you have any additional info on the USB VBUSCLMP pin. The manual says that it is the divided down Vbus. What is the divisor? The P1010 RDB schematic has a diode protecting this pin. What are the critical specifications for the diode?
The diode was supposed to be used for in OTG mode. Since the USB phy in P1010 doesn't support OTG, you may choose to ignore it. The VBUS operates at 5V. But VBUSCLMP operates at 3.3V. So you should implement a potential divider to bring down 5V to 3.3V as shown in RDB.
In case using on-chip USB PHY, low-speed mode is not supported at all? Or it can be supported if operating in "Host" mode?
Low-speed mode (LS) is supported in Host mode but not in device mode.
Can you tell me whether USB internal PHY on P1010 supports UTMI+ Level3 or not?
UTMI+ Level3 is supported in P1010
Please advise how power supply to USB port should be controlled when using on-chip USB PHY. Without controlling through IFC bus (via CPLD) like P1010RDB schematic, is there other way to control for it?
DRVVBUS should be used to control the external VBUS supply. By mistake this signal has been shown as a ULPI signal in P1010 RM because of which P1010RDB designer have not used it for externals VBUS control.
About USBVDD1_8(J21,K21), on HWspec Table1 Notes 20 says that "20.This pin should be connected to Vss through 1μF.No need to supply power to this pin. 1.8V output may be observed on this pin during normal working conditions." Is it okay to tie J21 and K21 pins together and connect to Vss via a "single" 1uF capacitor? Or 1uF cap is required for each pin respectively?
It should be okay to combine both the pins and connecting to Vss via single 1uF capacitor.
If the whole USB (controller and PHY) is not used, user still needs to supply USBVDD3_3 power, Right? What is the reason?
Yes it is required to provide USBVDD3_3 even if USB controller and PHY are not used at all. This is a requirement from design to keep the logic in a sane state.
If the whole USB is not used, does user need to follow power sequencing of USBVDD3_3, assuming USBVDD3_3 supply needs to be present?
Following the sequence between USBVDD3_3 and other 3.3V supplies is not required.
It is must to provide supply to USBVDD3_3 even if the USB PHY is not used. A suggestion, if USB PHY is not used customer can supply this pin with the same regulator which would be used to supply other 3.3V supply pins of SoC. Make sure that the ramp rate constraint is still followed for USBVDD3_3.