The eFlexPWM dithering feature FOR MC56f84xxx AND MC56f82xxx

Document created by xiangjun.rong Employee on Jul 15, 2015Last modified by ebiz_ws_prod on Dec 13, 2017
Version 4Show Document
  • View in full screen mode

For switch mode power supply application, the output voltage resolution is dependent on PWM resolution, the PWM resolution is dependent on the PWM module driving clock(IP Bus clock) frequency and PWM signal output frequency.  But the eflexPWM module has Fraction Delay logic feature, which is equivalent to increase the PWM module driving clock frequency.

For the MC56F847xx, there are two eFlexPWM modules: eFlexPWMA  and eFlexPWMB, the eFlexPWMA supports fractional Delay logic with micro-edge placement.  The eFlexPWMB module does not support the fractional Delay logic with micro-edge placement, but the eFlexPWMB module can use dithering to simulate the fine edge control, the mode is called ”Fraction Delay Logic without Micro-Edge Placement Block”.

Although the Reference Manual of MC56F847xx does not list the fractional registers, but they exist exactly. For example, PWMB_SMxFRACVAL1,  PWMB_SMxFRACVAL2, PWMB_SMxFRACVAL3, PWMB_SMxFRACVAL4, PWMB_SMxFRACVAL5 and PWMB_SMxFRACTRL exist.

The dithering means that the PWM duty cycle can increase or decrease one out of N PWM cycles, the N is dependent on the fraction value defined in the PWMB_SMxFRACVALy register, for example if the PWMB_SM0FRACVAL4 is 0x4000, the fraction equals to 8/32=1/4, it means that the duty cycle of one PWM cycle  out of four PWM cycles will increase by one.

The dithering mode does not need to enable internal PLL module of eFlexPWM.

Configuration:

Setting the corresponding bits in PWMB_SMxFRACTRL register, then write the  PWMB_SMxFRACVAL1,  PWMB_SMxFRACVAL2, PWMB_SMxFRACVAL3, PWMB_SMxFRACVAL4, PWMB_SMxFRACVAL5 registers, it is okay.

              PWMB_SM0FRCTRL=0x04;

              PWMB_SM0FRACVAL3=0x2000;

The PWMB module configuration:

PMB_SM0VAL2= PWMB_SM0VAL4, PWMB_SM0VAL3= PWMB_SM0VAL5, and PWMB_SM0CTRL2=0x2000;

PWMB_SM0FRCTRL=0x04;

PWMB_SM0FRACVAL3=0x2000;

 

With the above figuration, the PWMB_SM0 is set up in independent mode, and the PWMB_A0 and PWMB_B0 should have the same waveform if there is not fractional feature.

After the fractional Delay logic with dithering sub mode is enabled, the duty cycle of one PWM cycle out of 8 PWM cycle is different.

 

 

In the figure, two channels PWMB_A0 and PWMB_B0 are displayed, because the two signals almost have the save waveform, so they are superimposed most of time, but there are two cycle which are different. The Yellow channel on the oscilloscope  is pin 23 of J503( GPIOG2 or  PWMB-B0) signal, the pink channel is pin24 of J503(GPIOG3 or  PWMB_A0 )signal.

You can see one one duty cycle among 8 PWM cycle is different.

BR

XiangJun Rong

Original Attachment has been moved to: ditherPWMB84789_1.rar

Attachments

    Outcomes