• JTAG test issue on Vybrid MVF50NS151CMK40

    Hello,   I made a boundaryscan project for a board with a Vybrid module MVF50NS151CMK40 using the "Cascon" tools from Göpel electronic. I have a bad answer when I read the ID register: Cascon tools reads 01...
    Luc Dalongeville
    last modified by Luc Dalongeville
  • WM8974 codec setup

    Hi, I have a custom board using Vybrid processor. We are trying to add audio support using WM8974 codec, using i2c + i2c IC codec seems to be working (i2cdetect shows is at 0x1A) However, Im not sure about changes...
    Leonardo Giordano
    last modified by Leonardo Giordano
  • Vybrid eSDHC Controller

    I am trying to get a simple SDHC driver to work using the A5 core of the Vybrid processor. The board is a custom, however I know that both the board and the card are functional as I can use a Freescale driver and both...
    Ken Green
    last modified by Ken Green
  • Vybrid PLL3 PFD3

    I am trying to use PLL3 PFD3 clock as the source for the eSDHC1 clock. The problem is getting the PLL3 PFD3 functional. I am doing the following: - Check ANADIG_PLL3_LOCK to verify that PLL3 is running and locked ...
    Ken Green
    last modified by Ken Green
  • Yocto Pyro Fails to build

    Hi,   I have Ubuntu 18.04.2 LTS. I have installed Yocto Pyro. I can get it to build for my iMX SabreLite OK and now I need to build an SDCard image for my Vybrid TWR-VF65GS10 system. I do:   cd fsl MACHIN...
    Richard Copeman
    last modified by Richard Copeman
  • Vybrid (vf610) QSPI HW issues

    Dear Community,   I'd like to ask for two QSPI specific issues:   1. In the current Linux kernel driver - there is a comment regarding the QSPI working in "IP Command Read" mode: Linux source code: driver...
    Łukasz Majewski
    last modified by Łukasz Majewski
  • Vybrid (vf610) Chip Errata document

    Dear Community,   I would like to ask if there is a "Chip errata" document for Vybrid (e.g. vf610)? I'm asking since there are some issues with DMA usage with DSPI controller and also QSPI controller HW issues ...
    Łukasz Majewski
    last modified by Łukasz Majewski
  • The "sdhci-esdhc-imx: probe of 400b1000.esdhc failed with error -22" message.

    Hello We have the board that has wl1837 connected to esdhc0 of vybrid vf6xx via the 1.8 V - 3.3 V transformer. My image is based on timesys linux kernel 3.13. When booting up, the kernel gives me: "sdhci-esdhc-imx: p...
    lyudmila voronina
    last modified by lyudmila voronina
  • Changing attributes for different memory regions

    Hi Experts,   Is it possible to change the memory attributes for different memory regions for Cortex-M4 core in HALO processor MAC57d5xx? As mentioned in the reference manual, the default attributes for different...
    Zubair Mohiuddin
    last modified by Zubair Mohiuddin
  • Device tree creation for the vybrid vf6xx processor and mv88E3019 (Marvell).

    Hello   I rebuilt Linux kernel 3.13 with Marvell drivers and created booting SD card for our device with vybrid vf6xx on board. Now it is necessary to start network. I created device tree for FEC ( I took TWR-...
    lyudmila voronina
    last modified by lyudmila voronina
  • Are there special programs for simplification  or automation of device tree creation for the vybrid vf6xx processor?

    Hello We bought several  vybrid vf6xx processor and developed the device. We have Linux kernel 3.13 from Timesys for TWR-VF65GS10. Now we want to build  Linux kernel 3.13 for our device, bu...
    lyudmila voronina
    last modified by lyudmila voronina
  • how to create library project?

    How to create new library project?
    Ashwini Machha
    last modified by Ashwini Machha
  • Does somebody know the stable toolchain, when the booting continues to function both over the SD card and over TFTP after rebuilding of the 3.13 kernel?

    Hello   We have Linux kernel 3.13 from Timesys for TWR-VF65GS10. I built Linux kernel 3.13 with different versions of toolchain on webfactory and all the time I receive different results. There were such...
    lyudmila voronina
    last modified by lyudmila voronina
  • Vybrid QSPI boot flow

    I'm hoping someone up out there is familiar with the boot up flow of the Vybrid processor.  I have an OTS SOM that will be booting the A5 core from QSPI flash (located on the SOM) in DDR x2 mode, with the code en...
    Ken Green
    last modified by Ken Green
  • Vybrid VF50 BootROM fuse bank CRC checking

    Hi, we use SoC module Colibry VF50 produced by Toradex - module contains VF50 MPU, a NAND flash and a DDR3 ram. With original configuration from Toradex the MPU works properly. Original configuration uses ext.oscila...
    Jan Simak
    last modified by Jan Simak
  • Vybrid IAR Boot File

    Basically this is a question on creating a binary file using the IAR IDE that can be booted from QSPI flash. I asked IAR on how to do this since the issues are on using their IDE, however they want money (purchase a s...
    Ken Green
    last modified by Ken Green
  • TWR-VF65GS10(VF610) can't get network access in U-boot

    Hi   I am using a TWR-VF65GS10 (VF610) and have built u-boot from these two repositories:   https://github.com/u-boot/u-boot https://github.com/Freescale/u-boot-fslc.git   I build u-boot ...
    Mauricio Agurto
    last modified by Mauricio Agurto
  • Vybrid: Problem with DDR3 gate training

    Dear All,   This is a somewhat a follow up question for: Vybrid: About DDR leveling feature on DDRMC.  [1]   I've managed to run the RDLVL training (and receive results similar to expected one). Unf...
    Łukasz Majewski
    last modified by Łukasz Majewski
  • Vybrid : Setting core supply when executing SW RESET

    Dear Sir   I would like to ask about the STEPs for the SW Reset.   I refer to the following community and AN4807 Rev.0, 10/2013. https://community.nxp.com/message/522684?q=Vybrid%20SW_RST Customers ref...
    Eishi Shibusawa
    last modified by Eishi Shibusawa
  • Vybrid initialization sequence

    Dear Sir   I would like to ask about the initialization sequence of Vybrid.   Customer is executing with the following steps. 1.Clock initializaion; 2.UART initialization; 3.LPDDR iomux initialization...
    Eishi Shibusawa
    last modified by Eishi Shibusawa