• JTAG test issue on Vybrid MVF50NS151CMK40

    Hello,   I made a boundaryscan project for a board with a Vybrid module MVF50NS151CMK40 using the "Cascon" tools from Göpel electronic. I have a bad answer when I read the ID register: Cascon tools reads 01...
    Luc Dalongeville
    last modified by Luc Dalongeville
  • Vybrid: Problem with DDR3 gate training

    Dear All,   This is a somewhat a follow up question for: Vybrid: About DDR leveling feature on DDRMC.  [1]   I've managed to run the RDLVL training (and receive results similar to expected one). Unf...
    Łukasz Majewski
    last modified by Łukasz Majewski
  • I want to connect FPGA and Vybrid with 32bit data bus

    Hello,   I want to connect FPGA and Vybrid with 32bit data bus and over 10bit address (acting like SRAM).   Vybrid series have 32-bit flexbus but must use multiplexing address and data.   If ddr...
    Jinseok Kim
    last modified by Jinseok Kim
  • Vybrid / Vivante GPU displays gradient too dark

    Hi,   it seems that I found a problem concerning the Vivante GPU or driver stack when using OpenVG radial gradient.   The attached example code (based on the tiger example of the 0.5.0 OpenVG driver and MQ...
    Dirk Doerr
    last modified by Dirk Doerr
  • How to test,debug vybrid qspiXIP bootloader project

    Dear Sir/Madam, Hello,   We are developing a VF3x based prototype with MQX, with DS-5. I have added a square wave generation SW on a GPIO pin of VF3x of the MQX I2C project. Tested it with DS-5 debugger, and th...
    Mehmet Ali Ipin
    last modified by Mehmet Ali Ipin
  • Vybrid DCD DDR initialization

    Hi Everyone Im trying to get a basic MQX project based on examples/hello booting from QSPI flash on Freescale Vybrid Tower module. I have succeeded booting it from QSPI flash and running the code from internal RAM, h...
    igor-imx
    last modified by igor-imx
  • Vybrid PIT DMA Triggers

    Hello All,   I see in the VF6xx data sheet that the PIT is supposed to be able to trigger DMA requests.  However, the documentation for this seems to be lacking.   Does anyone have an example of start...
    Nathan Barrett
    last modified by Nathan Barrett
  • Vybrid DDR memory addressing

    Hello,   I'd like to know DDR memory addressing of Vybrid, because we have to check memory contents is correct or not. I saw the DDr memory addressing map like below. Does this means when data write/read to ...
    Toshishisa Sugiyama
    last modified by Toshishisa Sugiyama
  • Vybrid NAND boot

    Hi Im trying to get some information on how to flash u-boot, Linux kernel and rootFS onto nand chip for the Freescale Vybrid Tower module. I found a document on the timesys website with instructions on how to flash...
    igor-imx
    last modified by igor-imx
  • Vybrid RD_DL_SET

    Hi, We tested memory timing DDR validation tool. We heard we can use fixed value for RD_DL_SET=4 and GATE_CFG=0 regardless of the result of DDR validation results. However, the result of RD_DL_SET shows good v...
    Toshishisa Sugiyama
    last modified by Toshishisa Sugiyama
  • About DCU IOMUX switching during TFT display of Vybrid.

    Dear community.   Our customer has question below.   Is it possible to switch the IOMUXC DSE of DCU during TFT  indication . Please let me determine if the issue of flickering occurs. A changed regis...
    Takashi Takahashi
    last modified by Takashi Takahashi
  • Adding IMAXAI2ETH (eth daughter board) to EVB-VF522R3

    Hello Guys, I have an EVB-VF522R3 board and IMXAI2ETH-SMSC board (SCH-28039 REV A1).   I want to load application to board via eth in u-boot. I think u-boot is all set to get the data over eth but board needs t...
    gohilurvish
    last modified by gohilurvish
  • Configurable interval of DMA_ACT of Vybrid.

    HI community. Our customer has question below.   About  the configurable interval of DMA_ACT. Is it correct my understanding of the below comments.   Vybrid RM description . 57.5.10 DMA and De-inte...
    Takashi Takahashi
    last modified by Takashi Takahashi
  • DDRv_results_revG_x_revH_TVR-VF65.xlsx

    Valid ranges of tuning parameters for different setting of CR132, PHYs ... /Jiri
    jiri-b36968
    last modified by jiri-b36968
  • Pin FMEA of Vybrid

    Dear community. Our customer has question below.   1, In power supply group, Pin Out single use only of the terminal (below exported terminal) Would you please tell me the operation at the time of open failure....
    Takashi Takahashi
    last modified by Takashi Takahashi
  • Unable to get console for booting from sdcard

    Hello ,      I am using Vf5xxR series board. I want to boot it from sdcard. I have done following jumper setting on the board.        In order to boot from the SD interfa...
    Shrikant Chikodikar
    last modified by Shrikant Chikodikar
  • Chip doesn't seem to work correctly with this BSDL files "Vybrid F Series 364MAPBGA BSDL Silicon Revision 1.1 (REV 0) " or "bga_364_v2.bsdl"

    Hi, it seems that I have the same problem like " Debugging BSCAN test for Vybrid. Chip doesn't seem to respond correctly with this BSDL file  " resp. "Vybrid VF60 no output in JTAG boundary scan" .   Is th...
    Veges Andreas
    last modified by Veges Andreas
  • DCU_layer_transfer_issue_3.pdf

    jiri-b36968
    last modified by jiri-b36968
  • BSDL File for VF5xxR

    @Richard Stulens   Hi Richard,   With the Cascon tool from Göpel electronic I can program an external EEProm (M95256WMN6). But it seems, that the BSDL File which I found ("Vybrid F Series 364MAPBGA B...
    Veges Andreas
    last modified by Veges Andreas
  • IS there an Android build for Vybrid available - BSP, doc, etc - similar to what was done for iMX processors?

    Thanks Larry
    larry ciummo
    last modified by larry ciummo