• Vybrid VF50 BootROM fuse bank CRC checking

    Hi, we use SoC module Colibry VF50 produced by Toradex - module contains VF50 MPU, a NAND flash and a DDR3 ram. With original configuration from Toradex the MPU works properly. Original configuration uses ext.oscila...
    Jan Simak
    last modified by Jan Simak
  • Vybrid: Problem with DDR3 gate training

    Dear All,   This is a somewhat a follow up question for: Vybrid: About DDR leveling feature on DDRMC.  [1]   I've managed to run the RDLVL training (and receive results similar to expected one). Unf...
    Łukasz Majewski
    last modified by Łukasz Majewski
  • Vybrid : Setting core supply when executing SW RESET

    Dear Sir   I would like to ask about the STEPs for the SW Reset.   I refer to the following community and AN4807 Rev.0, 10/2013. https://community.nxp.com/message/522684?q=Vybrid%20SW_RST Customers ref...
    Eishi Shibusawa
    last modified by Eishi Shibusawa
  • Vybrid initialization sequence

    Dear Sir   I would like to ask about the initialization sequence of Vybrid.   Customer is executing with the following steps. 1.Clock initializaion; 2.UART initialization; 3.LPDDR iomux initialization...
    Eishi Shibusawa
    last modified by Eishi Shibusawa
  • RESET pin

    Dear Sir   I refer to the VYBRIDFSERIESEC Rev.9. It is described as the follows at P69 NOTE. "RESET pin has a external weak pull UP requirement if LPDDR2 memory is required to support content retention in the...
    Eishi Shibusawa
    last modified by Eishi Shibusawa
  • UART register description missing

    In the Vybrid Reference Manual Rev. 7 (06/2014) the following registers have been part of chapter 49 (UART): UARTx_C5 UARTx_MODEM UARTx_WP7816T0   In Rev. 8 (11/2015) and newer Vybrid Reference Manu...
    Stefan Agner
    last modified by Stefan Agner
  • workaround for e8052 (RMII)

    Dear Sir   I want to ask the workaround for e8052. It is described  at 12.3.0.2 Internal RMII reference clock in VYBRIDHDUG Rev.1. I want to confirm the workaround based on "EXTERNAL CLOCK SOURCE" scheme...
    Eishi Shibusawa
    last modified by Eishi Shibusawa
  • I want to connect FPGA and Vybrid with 32bit data bus

    Hello,   I want to connect FPGA and Vybrid with 32bit data bus and over 10bit address (acting like SRAM).   Vybrid series have 32-bit flexbus but must use multiplexing address and data.   If ddr...
    Jinseok Kim
    last modified by Jinseok Kim
  • LAN Trouble (probably concerned with Vybrid errata e6358 )

    Dear forum members,     We are facing LAN trouble now. We are using Vybrid VF5 chip and Timesys Linux(3.0) on our prototype.We think the trouble relates to Vybrid errata e6358. The symptom is as follows: &...
    Makoto Katsukura
    last modified by Makoto Katsukura
  • Vybrid TWR-VF65 debug

    Dear Vybrid users,   TWR-VF65 rev. H can be debugged by: on-board OpenSDA. CMSIS-DAP application needed. Default Virtual serial port application loaded. CMSIS-DAP + Virtual serial port application attached for ...
    jiri-b36968
    last modified by jiri-b36968
  • I/O IRQ conflict

        Hello,   I'm porting  old timesys BSP to the new Yocto Jethro, we use a 7" LCD panel with egalax touch screen device (like i.MX6 sabre design). We use the freescale egalax driver with bi...
    Nouchi
    last modified by Nouchi
  • How to test,debug vybrid qspiXIP bootloader project

    Dear Sir/Madam, Hello,   We are developing a VF3x based prototype with MQX, with DS-5. I have added a square wave generation SW on a GPIO pin of VF3x of the MQX I2C project. Tested it with DS-5 debugger, and th...
    Mehmet Ali Ipin
    last modified by Mehmet Ali Ipin
  • Vybrid DCD DDR initialization

    Hi Everyone Im trying to get a basic MQX project based on examples/hello booting from QSPI flash on Freescale Vybrid Tower module. I have succeeded booting it from QSPI flash and running the code from internal RAM, h...
    igor-imx
    last modified by igor-imx
  • Freescale USB Stack and Vybrid

    Hello   There's no dedicated community for this USB stack. There's also no support for Vybrid (yet?). In case anyone wants to try it now (footprint or something else), here's my attempt to port virtual_camera de...
    Edward Karpicz
    last modified by Edward Karpicz
  • Updated CMSIS-DAP application

    Attached is the latest OpenSDA CMSIS-DAP app from ARM.   It's built to run on top of the OpenSDA bootloader, so place your revision G Tower board (earlier versions not supported) in bootloader mode and drag and ...
    Ross Mcluckie
    last modified by Ross Mcluckie
  • Vybrid PIT DMA Triggers

    Hello All,   I see in the VF6xx data sheet that the PIT is supposed to be able to trigger DMA requests.  However, the documentation for this seems to be lacking.   Does anyone have an example of start...
    Nathan Barrett
    last modified by Nathan Barrett
  • UART framing errors do not get cleared

    We have a communication running over UART and we have issues with clearing framing errors.   If we communicate normally and do do not generate to many errors then we can clear S1[FE] flag without issues. ( we cl...
    Pivk Luka
    last modified by Pivk Luka
  • IEEE 1588 PTP source code for MQX 4.2 on TWR-VF65GS10

    Hi   I have the TWR-VF65GS10 board. I am running MQX 4.2 on the Vybrid processor on the Tower. MQX 4.2 contains a demo application for IEEE 1588. The demo application stops working after 4 hours. Is it possible ...
    Daniel Basilio
    last modified by Daniel Basilio
  • Vybrid NAND boot

    Hi Im trying to get some information on how to flash u-boot, Linux kernel and rootFS onto nand chip for the Freescale Vybrid Tower module. I found a document on the timesys website with instructions on how to flash...
    igor-imx
    last modified by igor-imx
  • Vybrid multiple resets

    We use the KVF61NS152CMK50, but only the A5 core is used. We observed some very strange behavior on the reset line after a short 3.3V dip  – see attached. Blue trace is 3.3V, Yellow is /RESET   ...
    Shoumin Liu
    last modified by Shoumin Liu