• UART framing errors do not get cleared

    We have a communication running over UART and we have issues with clearing framing errors.   If we communicate normally and do do not generate to many errors then we can clear S1[FE] flag without issues. ( we cl...
    Pivk Luka
    last modified by Pivk Luka
  • MCC support for kernel 4.1

    Hello,   Multi-Core Communication  functionnalities will be supported in 4.1 kernel?   Regards, Emmanuel
    Nouchi
    last modified by Nouchi
  • IEEE 1588 PTP source code for MQX 4.2 on TWR-VF65GS10

    Hi   I have the TWR-VF65GS10 board. I am running MQX 4.2 on the Vybrid processor on the Tower. MQX 4.2 contains a demo application for IEEE 1588. The demo application stops working after 4 hours. Is it possible ...
    Daniel Basilio
    last modified by Daniel Basilio
  • Vybrid NAND boot

    Hi Im trying to get some information on how to flash u-boot, Linux kernel and rootFS onto nand chip for the Freescale Vybrid Tower module. I found a document on the timesys website with instructions on how to flash...
    igor-imx
    last modified by igor-imx
  • Vybrid HAB Setup

    Hello,   We are utilizing the Vybrid VF6xxx processor and have requirements to support HAB for our application.  Are there any app-notes or how-to's related to HAB specifically related to the Vybrid?  ...
    rmcginnis
    last modified by rmcginnis
  • Reset A5 without interfering on M4

    Hello!   Our customer has a somehow tricky question, I couldnt find an obvious answer:   Imagining the core configuration on the TWR card, where cortex A5 is master and M4 is slave.   Would it be pos...
    Bruno Castelucci
    last modified by Bruno Castelucci
  • gator problem

    Timesys Support:     I'm using twr-vf65gs10. I have built the os(timesys) on the board. I want to connect to the Streamline(DS-5), but the gator version is not supported. So, how to update the gator v...
    Johnny Wick
    last modified by Johnny Wick
  • Processor expert project for the Vybrid Tower board TWR-VF65GS10

    Is there a Processor Expert sample project for the Vybrid Tower board TWR-VF65GS10?
    adiroot
    last modified by adiroot
  • Peripheral Software Libraries for Vybrid Processors - using TWR-VF65GS10

    Hi All,   I have just started using Vybrid controller and quit new to Asymmetric Multiprocessor environment. I am looking for some sample examples or some sample code from which I can have basic idea about how s...
    Harshad Lele
    last modified by Harshad Lele
  • DDRv_results_revG_x_revH_TVR-VF65.xlsx

    Valid ranges of tuning parameters for different setting of CR132, PHYs ... /Jiri
    jiri-b36968
    last modified by jiri-b36968
  • Vybrid VF6xx Cortex-A5 and Cortex-M4 wake up and sleep overhead 

    I want to measure the wake up and sleep time latency of both Cortex-A5 and Cortex-M4, but my power scope can only get me 10us for sleep and wake up overhead for Cortex-M4, not to mention Cortex-A5   I want more ...
    a a
    last modified by a a
  • Vybrid Cortex-M4 Bare Metal L1 Data Cache disable and enable

    When using Vybrid Cortex-M4 bare metal debug, can L1 data cache being disabled? where should I change the setting? And here're two questions, what's the data cache and instruction cache miss penalty in Systicks ? Is...
    a a
    last modified by a a
  • Cache, set associate to direct mapped

    I read this on the ARM programmer guide "You can lock the replacement algorithm on a way basis, enabling the associativity to be reduced from eight-way down to one-way, direct mapped."   Register 9 is the lock...
    a a
    last modified by a a
  • Vybrid Cortex-A5 cache access latency

    On "Understand Vybrid Architecture" cache access latency Processor registers 1 cycle On-chip L1 cache 1-2 cycles On-chip L2 cache 8 cycles Main memory, L3, dynamic RAM  30-100 cycles Back-up memory, hard dis...
    a a
    last modified by a a
  • MCC Cpu-to-CPU interrupt cycle time

    Hi, I am now using TWR-VF65SG10, and I try to measure the cycle time of MCC cpu-to-cpu interrupt, How much cycle it takes between M4 triggers an interrupt and A5 receives an event? Since I can't use Streamline, and...
    a a
    last modified by a a
  • L2 cache, TCM enable

    Hi, I am using TWR-VF65GS10, I want to check whether L2 cache is enabled or not, I found BT_MMU_DISABLE and L2_CACHE_DISABLE in reference manual, but I don't actually know how and where to use it. And I also want t...
    a a
    last modified by a a
  • Change u-boot in TWR-VF65GS10

    I am now using TWR-VF65GS10 and I want to change the bootloader so that I can boot new image, but I don't know where to put my new u-boot, I found a step in Timesys Getting Started Guide and Booting the Freescale Vybr...
    a a
    last modified by a a
  • TWR-VF65GS10 device tree

    Hi, I tried to build lunix kernel with gator driver and file system from ll5 web page, but it didn't work, so I tried to get the kernel source and rebuild it. And here is the question, how can I add gator to device ...
    a a
    last modified by a a
  • Trace on Vybrid with DS-5

    I am now using TWR-VF65SG10 Tower Board , and I can boot from SD card, by the way I am on windows host   I'm trying to use DS-5 to trace on this board, and I follow the step as follow link   https://www.goog...
    a a
    last modified by a a
  • About vybrid Nand driver

    Hello,   I'm looking for a tricky solution, here is my problem: I want to make devices field update linux kernel 3.0.15-ts-armv7l to a newer version using nand tools. But, u-boot is 2013.07 from timesys and us...
    Nouchi
    last modified by Nouchi