• Vybrid (vf610) QSPI HW issues

    Dear Community,   I'd like to ask for two QSPI specific issues:   1. In the current Linux kernel driver - there is a comment regarding the QSPI working in "IP Command Read" mode: Linux source code: driver...
    Łukasz Majewski
    last modified by Łukasz Majewski
  • Vybrid (vf610) Chip Errata document

    Dear Community,   I would like to ask if there is a "Chip errata" document for Vybrid (e.g. vf610)? I'm asking since there are some issues with DMA usage with DSPI controller and also QSPI controller HW issues ...
    Łukasz Majewski
    last modified by Łukasz Majewski
  • Changing attributes for different memory regions

    Hi Experts,   Is it possible to change the memory attributes for different memory regions for Cortex-M4 core in HALO processor MAC57d5xx? As mentioned in the reference manual, the default attributes for different...
    Zubair Mohiuddin
    last modified by Zubair Mohiuddin
  • VF6xx with a uSD XC 8GB

    Hello,   Is VF6xx able to access a uSD XC? I don't know if it possible to access it.   No problem with microSDHC but what happens with a 8GB microSDXC   Thank you very much
    JOSE LOPEZ
    last modified by JOSE LOPEZ
  • Conflict in IO MUX Configuration for i.MX6 Dual processor

    Hello All,   I have problem in configuring the IO Mux pads, when I try to use these particular signals: SD4_CMD (B17) & SD4_CLK (E16) NAND_RE_B (B17) & NAND_WE_B (E16)   Since, I have to use both...
    Ram Manohar
    created by Ram Manohar
  • DDR stress test for Vybrid / TWR-VF65GS10

    Hi,   I would like to test and tune up my DDR3 memory on my Vybrid board. Our CPU board is strongly similar to TWR-VF65GS10 (including most part numbers). I use IAR system with MQX 4.2.   I have already ...
    Sandro Bastos
    last modified by Sandro Bastos
  • Processor expert project for the Vybrid Tower board TWR-VF65GS10

    Is there a Processor Expert sample project for the Vybrid Tower board TWR-VF65GS10?
    adiroot
    last modified by adiroot
  • Vybrid VF6xx Cortex-A5 and Cortex-M4 wake up and sleep overhead 

    I want to measure the wake up and sleep time latency of both Cortex-A5 and Cortex-M4, but my power scope can only get me 10us for sleep and wake up overhead for Cortex-M4, not to mention Cortex-A5   I want more ...
    a a
    last modified by a a
  • Vybrid Cortex-M4 Bare Metal L1 Data Cache disable and enable

    When using Vybrid Cortex-M4 bare metal debug, can L1 data cache being disabled? where should I change the setting? And here're two questions, what's the data cache and instruction cache miss penalty in Systicks ? Is...
    a a
    last modified by a a
  • Cache, set associate to direct mapped

    I read this on the ARM programmer guide "You can lock the replacement algorithm on a way basis, enabling the associativity to be reduced from eight-way down to one-way, direct mapped."   Register 9 is the lock...
    a a
    last modified by a a
  • Vybrid Cortex-A5 cache access latency

    On "Understand Vybrid Architecture" cache access latency Processor registers 1 cycle On-chip L1 cache 1-2 cycles On-chip L2 cache 8 cycles Main memory, L3, dynamic RAM  30-100 cycles Back-up memory, hard dis...
    a a
    last modified by a a
  • Vybrid M4 hangup when using initialized structs

    The following code crashes on my Vybrid M4. The code is not even executed, but mqxboot already crashes the Linux kernel when uploading the binary.   struct xxx {     int a;     in...
    mpfgregory
    last modified by mpfgregory
  • Is there a DDR3 stress test tool for the Vybrid processors?

    Is there a DDR3 stress stress/calibration tool for the Vybrid processors like the i.MX6 tool?
    James Herrera
    last modified by James Herrera
  • Vybrid LPDDR2-configuration - IS43LD16640A

    We are currently attempting to configure an LPDDR2-chip (ISSI IS43LD16640A).   Seing as we currently work on a Linux host system, we have attempted to do the config manually, taking inspiration from the followin...
    Thomas Fredriksen
    last modified by Thomas Fredriksen
  • PEx for Vybrid board with MQX

    Hi,   I am quite new to the community and to the Freescale (NXP) boards in general, so hope my question is not too trivial. We are using DS-5 v5.20.1, TWR-VF65GS10 and want to use A5 core with MQX4.2. Hovewer, ...
    klimat
    last modified by klimat
  • Vybrid DDR3 Tuning

    The Vybrid needs a way to calibrate DDR3 settings after using Processor Expert to determine all the base-line register settings.  Something like the i.MX6/7 stress tester.  Will someone please point me to a ...
    Antonio Jenkins
    last modified by Antonio Jenkins
  • Calculating Vybrid CPU core temperature with the internal temperature sensor

    Hi!   At the moment the internal temperature sensor readings are calculated using the formula[ Temp = 25 - ( (Vtemp -Vtemp25) / m) ] with optimal slope-coefficient constant at all temperatures provided in Vybri...
    Bhuvanchandra DV
    last modified by Bhuvanchandra DV
  • 32-Bit DMA Transfer Not Correctly Functioning

    Hello All,   I'm currently trying to do a DMA transfer into an eDMA register related to an SPI transfer and it does not seem to be correctly working for some reason.  This is on a Vybrid VF6XX processor. &#...
    Nathan Barrett
    last modified by Nathan Barrett
  • Error when attempting to install 10.4 Microcontroller Drivers Suite in latest DS-5

    I just received my Vybrid Tower Kit. I installed the latest version of DS-5 (5.22). When attempting to install 10.4 Microcontroller Drivers Suite for Processor Expert support, the install fails.   An error occ...
    dachancellor
    last modified by dachancellor
  • Changing the operating mode of A5 core and implementing CPU to CPU interrupt in mcc

    Hello,   a) Changing the operating behaviour of A5 core => We are running linux on Cosmic Phytec VF6XX board, in order to reduce the power consumed by the board, we require A5 core to switch to ultra-low pow...
    gurdeepak joshi
    last modified by gurdeepak joshi