• MQX Plug-in not compatible with DS-5.18

    Hi all,   The recent DS-5.18 update included an update to the Eclipse version, this unfortunately has caused problems with the MQX plug-in.   The attached is an updated plug-in that is required if you wish...
    Ross Mcluckie
    last modified by Ross Mcluckie
  • How to connect TWR-VF65GS10 to DSTREAM with DS-5?

    Hi, I've got a TWR-VF65GS10-KIT recently, and I am trying to connect it to the DSTREAM with DS-5 to do some debugging work. I tried to connect the board to DSTREAM with either the K20 JTAG Header (J2) or the Vybird J...
    Zhenyu Ning
    last modified by Zhenyu Ning
  • How to setup Ethernet hardware on the VF61 Vybrid Phytec Cosmic+ Board under Timesys Linux ?

    Respected Colleagues, Timesys Support, Karina Valencia Aguilar,   the Ethernet connection is now on the table.   I can connect VF61 Vybrid Phytec Cosmic+ Board to the Windows PC only trough USB RNDIS. ...
    Dragan Kujovic
    last modified by Dragan Kujovic
  • DS-5 Vybrid Tower DRAM init Script

    The VYBRID_SAMPLE_CODE from the website includes an DRAM init Script for the DS-5 Debugger.   However it seems it doesn't correctly initialize the Vybrid Tower Samsung Memory.   I modified some register s...
    Hans-Peter Rosinger
    last modified by ebiz_ws_prod
  • Can somebody provide a working Vybrid DSPI sample code for any SPI chip under Timesys Linux ?

    Respected Colleagues and Bruno Castelucci   I have made modifications for Phytec Vybrid Cosmic+ Board to the board-pcl052.c file in the way that Bruno Castelucci did in the board-pcm052.c file (Discussion SPI Dr...
    Dragan Kujovic
    last modified by Dragan Kujovic
  • MQX application is not booting from QuadSPI_NAND flash

    I have developed an mqx based audio application using vybrid tower system.I am using DS5 for my development. I have flashed hello_world application to QuadSPI serial nand flash using quadspi_load application available...
    Abdul Nihad
    last modified by Abdul Nihad
  • [Vybrid]  Coremark baremetal porting

    Hello        I'm currently porting Coremark Benchmark to the vybrid VF6 to evaluate the performance of this SoC. I'm using the twr-vf65gs10 board. I first built it on Timesys linux and got a ...
    du Maugouer Brieuc
    last modified by du Maugouer Brieuc
  • Freescale USB Stack and Vybrid

    Hello   There's no dedicated community for this USB stack. There's also no support for Vybrid (yet?). In case anyone wants to try it now (footprint or something else), here's my attempt to port virtual_camera de...
    Edward Karpicz
    last modified by Edward Karpicz
  • Updated CMSIS-DAP application

    Attached is the latest OpenSDA CMSIS-DAP app from ARM.   It's built to run on top of the OpenSDA bootloader, so place your revision G Tower board (earlier versions not supported) in bootloader mode and drag and ...
    Ross Mcluckie
    last modified by Ross Mcluckie
  • IEEE 1588 PTP source code for MQX 4.2 on TWR-VF65GS10

    Hi   I have the TWR-VF65GS10 board. I am running MQX 4.2 on the Vybrid processor on the Tower. MQX 4.2 contains a demo application for IEEE 1588. The demo application stops working after 4 hours. Is it possible ...
    Daniel Basilio
    last modified by Daniel Basilio
  • gator problem

    Timesys Support:     I'm using twr-vf65gs10. I have built the os(timesys) on the board. I want to connect to the Streamline(DS-5), but the gator version is not supported. So, how to update the gator v...
    Johnny Wick
    last modified by Johnny Wick
  • how to use ne10 on vybrid with mqx

    Hello, I want to use FFT on vybrid with MQX.Then Compiler  is ds-5. I have notice the ne10 is for Android and Linux. How can I use the ne10 on my project? Is there some other DSP library I can use?
    ww p
    last modified by ww p
  • Vybrid DMA0, ENET0 vs DMA1, ENET1 and CA5 vs CM4

    Hello,   We are running Linux 3.13.9 on CA5 core and MQX 4.2.x on CM4 core.  Originally, we allowed Linux to take ETH0 and DMA0 (and DMAMUX0/1) and left ETH1 and DMA1 to CM4.  We are using an external ...
    SCOTT THOMPSON
    last modified by SCOTT THOMPSON
  • Peripheral Software Libraries for Vybrid Processors - using TWR-VF65GS10

    Hi All,   I have just started using Vybrid controller and quit new to Asymmetric Multiprocessor environment. I am looking for some sample examples or some sample code from which I can have basic idea about how s...
    Harshad Lele
    last modified by Harshad Lele
  • Vybrid VF6xx Cortex-A5 and Cortex-M4 wake up and sleep overhead 

    I want to measure the wake up and sleep time latency of both Cortex-A5 and Cortex-M4, but my power scope can only get me 10us for sleep and wake up overhead for Cortex-M4, not to mention Cortex-A5   I want more ...
    a a
    last modified by a a
  • Vybrid Cortex-M4 Bare Metal L1 Data Cache disable and enable

    When using Vybrid Cortex-M4 bare metal debug, can L1 data cache being disabled? where should I change the setting? And here're two questions, what's the data cache and instruction cache miss penalty in Systicks ? Is...
    a a
    last modified by a a
  • Cache, set associate to direct mapped

    I read this on the ARM programmer guide "You can lock the replacement algorithm on a way basis, enabling the associativity to be reduced from eight-way down to one-way, direct mapped."   Register 9 is the lock...
    a a
    last modified by a a
  • Vybrid Cortex-A5 cache access latency

    On "Understand Vybrid Architecture" cache access latency Processor registers 1 cycle On-chip L1 cache 1-2 cycles On-chip L2 cache 8 cycles Main memory, L3, dynamic RAM  30-100 cycles Back-up memory, hard dis...
    a a
    last modified by a a
  • MCC Cpu-to-CPU interrupt cycle time

    Hi, I am now using TWR-VF65SG10, and I try to measure the cycle time of MCC cpu-to-cpu interrupt, How much cycle it takes between M4 triggers an interrupt and A5 receives an event? Since I can't use Streamline, and...
    a a
    last modified by a a
  • L2 cache, TCM enable

    Hi, I am using TWR-VF65GS10, I want to check whether L2 cache is enabled or not, I found BT_MMU_DISABLE and L2_CACHE_DISABLE in reference manual, but I don't actually know how and where to use it. And I also want t...
    a a
    last modified by a a