Hello Support team, I have a question about S32K312 of HDQFP100 from the viewpoint of functional safety. [Questions] 1. VSS/V25/V11/VDD_HV_A has multiple pins, but are they connected internally? 2. If the VSS/V25/V11/VDD_HV_A pin fails with pin open, what are the concerns? 3. What are the concerns if the V25/V11 pin is shorted to VSS and fails? 4. If the VREFL/VREFH pin fails with pin open, what are the concerns? Best regards, Hiroyuki Kadowaki
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Hi Teams
Customer(BYD) have questions that what is specific safety goal for S32K3xx as SeooC. ,like MPC5746R as below:
Best Regards
Junjie
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I have reviewed the FMEDA excel data for the S32K312 MCU, and there are a few things to check, so I would like to request it. 1) The data I have is only applied in accordance with IEC-TR-62380 regarding Permanent Failure Rate. I would like to request that NXP provide me with the Failure Rate calculated using SN29500. 2) Among the failure rates predicted by IEC-TR-62380, the percentage of permanent die and package seems strange, so I would like to know the calculation conditions for permanent failure. (i.e. No of TR. 7.894E7, MOS, BiCMOS (low voltage) digital circuits, power 0.6W & Thermal resistance 35.3degC/W, package pin pitch 0.325, package width 10) Of the Permanent Total 130.4158 FIT, 0.4158 FIT was assigned to Die in FMEDA excel, and 130 FIT was assigned to Package. There is a difference from the actual calculation result according to IEC-TR-62380, so it is necessary to check whether the die calculation was calculated as Ton + Toff = 1 rather than Ton = 1.
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