• when accessing PCI physical address, T2080RDB hang

    When I read  PCI-0 physical address 0xf80000000(PCI-0 have no target device present) on T2080RDB(T2080E rev1.0) the CPU will hang and can not get CPU information from codeWarrior(codeWarrior report protocol&...
    Li Jun
    last modified by Li Jun
  • E5500 Core HID0 Register

    Hi,   I'm working on e5500 core, and have a question about HID0 representation difference between e5500 Core RM and BookE.   I'm tracking start.S file in arch/powerpc/cpu/mpc85xx directory of u-boot t...
  • How to test nvram rtc with powepc kernel

    Dear NXP,   I am working on T4240RDB-64B machine and using QORIQ-SDK-2.0 source. I needs to test NVRAM RTC in kernel. Needs to read and write the value.   Will you please tell me how to test&#...
    vinothkumar s
    last modified by vinothkumar s
  • Kernel Configuration in T4240RDB-64b

    Dear NXP,   I am working on T4240RDB-64B machine. I needs to add the driver kernel configuration. I am using QORIQ-SDK-2.0 source.   Which defconfig do I needs to take to enable the drive...
    vinothkumar s
    last modified by vinothkumar s
  • NVRAM RTC with T4240RDB-64b

    Dear NXP,   I am working on T4240RDB-64B machine. I needs to integrate NVRAM RTC (CY14B116M ) in build. I am using QORIQ-SDK-2.0 source.   Which one is suitable for this module or do I ne...
    vinothkumar s
    last modified by vinothkumar s
  • T1022 Clock Sequence

    Hi,   We are designing a custom board with a T1022 processor and would like to know if the there are any power-on sequencing requirements for the clocks?   Do all power rails need to be valid before clocks a...
    Bob Russell
    last modified by Bob Russell
  • [ERROR] PCI memory allocation (BAR Registers) on T1042D4RDB-64B

    Hello, My problem is briefly, PCI is not allocating memory on t1042d4-64b demo board. Below is the 'dmesg' messages and U-boot messages. I will be grateful for your helps. 'dmesg' messages from...
    Yusuf Altıparmak
    last modified by Yusuf Altıparmak
  • 1000Base-KX configuration in T1022

    Hi, Our serdes protocol is 0x87. We intend to configure serdes lane D in 1000Base-KX, i.e mac-2 which is SGMII 1G by default.   As per T1040 Manual Sec: 31.6.1.3 1000Base-KX, settings have been made. Here we ...
    Debdutta Banerjee
    last modified by Debdutta Banerjee
  • Need processor timings for DDR3 simulation in Hyperlynx

    HI! I am designing a custom board using T1042 processor. During the PCB designing of DDR3, i have to run some simulations on hyperlynx software using DDR batch simulation. i get all the results pass at 400 clock freq...
    Faiz Majeed
    last modified by Faiz Majeed
  • RCW Problem with T1024 new design

    We have a new design using a T1024 and are stuck.     The processor is connected to an FPGA on the IFC bus. We setup the RCW source to be 0_0010 0101, which should tell it to get the RCW from the IFC ...
    Joseph Vogl
    last modified by Joseph Vogl
  • T4240 Secure Boot - SCRATCHRW(n) Registers

    I am working on getting secure boot enabled and working on the T4240.   The manuals that I am referencing are:   QorIQ T4240 Family Reference Manual, Rev 1, 02/2015 Note that the latest version of that do...
    Arlen Baker
    last modified by Arlen Baker
  • T1040 FMAN Microcode

    Hi If i need to load the FMAN microcode to T1040RDB then i will copy the microcode from NOR flash to FMan controller Configuration Data Download Registers using the fm_upload_ucode function. The first step in the fm...
    kmanjushree@moog.com
    last modified by kmanjushree@moog.com
  • Multiple Ethernet Port in u-boot

    Dear NXP,   I am working on T4240RDB-64B machine.   I am using 8 Ethernet Port and able to ping single port at the time by using ethact command. I want to configure multiple Ethernet Port...
    vinothkumar s
    last modified by vinothkumar s
  • T2080 PVR Description

    In the T2080 Reference Manual, section 7.3.4.1 PVR mentions that the register is described in DCFG_CCSR_PVR (section 27.3.11). But the field descriptions don't match. In 7.3.4.1 it calls bits 24:27 the Processor Major...
    Scott Gerhold
    last modified by Scott Gerhold
  • T1040RDB FMAN Microcode

    Hi If i need to load the FMAN microcode to T1040RDB then i will copy the microcode from NOR flash to FMan controller Configuration Data Download Registers using the fm_upload_ucode function. The first step in the fm_u...
    kmanjushree@moog.com
    last modified by kmanjushree@moog.com
  • Remapping NOR Flash address in T1040D4RDB UBOOT

    Hi,   I'm trying to relocate default NOR Flash mapping in T1040D4RDB Uboot from 0xe8000000 to 0xF0000000. So as per the suggestion given in one of the post in NXP community, I modified CONFIG_SYS_FLASH_BASE as 0x...
    Amarnath MB
    last modified by Amarnath MB
  • USDPAA order restoration does not work

    Hi, I have a TCP/UDP performance problem while using T4240RDB and SDK 2.0 linux kernel. I am using the RDB board as a router, basicly the board is routing the traffic  received from eth0 to eth1. There is one i...
    ömer faruk er
    last modified by ömer faruk er
  • How can I build usdpaa-aps ?

    Hello,   I've cloned usdpaa-aps project from git address: git://git.freescale.com/ppc/sdk/usdpaa/usdpaa-apps.git. I run "make" but there were some errors. When I look at the standalone-env file I see some enviro...
    ömer faruk er
    last modified by ömer faruk er
  • T1022 SPI Boot

    Hi,   We are working on a custom board with a T1022 processor and would like to boot from SPI flash memory.   We require 128MB of memory but the processor only supports 24-bit addressing when booting from SP...
    Bob Russell
    last modified by Bob Russell
  • Compiling uImage with all linux modules

    Hello, I am trying to compile a new kernel obtained from GitHub - qoriq-open-source/linux (version 4.9) for t1042d4rdb-64b. using Yocto. I followed the steps;   1) bitbake virtual/kernel -c cleansstate 2) bit...
    Yusuf Altıparmak
    last modified by Yusuf Altıparmak