• T2080RDB cpu core hang problem

    Hello everyone,   We have hang problem in a scenario based on ipsec esp null with a custom board based on T2080 SoC with SDK 1.6. We are using a packet generator (IXIA) and generate internet mix packets for tes...
    ömer faruk er
    last modified by ömer faruk er
  • Port T1040 uio-seville  L2 switch API to mainline kernel

    Has anyone experience to compile the L2-Switch UIO-driver for T1040 ? I have successful compiled and running the mainline kernel 4.14 on my Board  from GitHub - Freescale/linux-fslc at 4.14.x+fslc  then i...
    Jörg Hering
    last modified by Jörg Hering
  • QorIQ T120 - DDR3 with T Topology

    In our Custom board design using QorIQ T1020 processor we have designed to use T Topology for DDR3 address/command/control and clock groups. Please confirm whether QorIQ processor supports T Topology for DDR3 as we h...
    Senthilkumar R
    last modified by Senthilkumar R
  • How to distribute packets to all cores with fmc rate limit ?

    Hello,   I'm trying to limit the frame rate on T2080RDB. I used this policy and config:   <netpcd xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="xmlProject/pcd.xsd...
    ömer faruk er
    last modified by ömer faruk er
  • Marvel Ethernet Switch connection issue with T1022 Processor

    We are having T1022 processor customized board , the SERDES configuration used in the RCW is 0x40.  The EC1 is connected to ethernet marvel switch (88E6320) port 5 with RGMII interface. Now we have initialised ma...
    Hemwant Rawat
    last modified by Hemwant Rawat
  • T2080 CGA_PLL1_RAT

    We are running SYSCLK at 100MHz. We are using PLL1 to drive the FMAN. We use Processor Expert to create the RCW. In the past I have been able to set CGA_PLL1_RAT to 7:1. But now it appears I cannot set it lower than 8...
    Scott Gerhold
    last modified by Scott Gerhold
  • T2080 PBI used to generate I2C traffic

    Is it possible in the PBI for the T2080 to issue I2C commands through the T2080s I2C UART. The registers for the I2C are in the CCSR space so they are accessible. We are not using the I2C for RCW, PBI or Boot. We are ...
    Scott Gerhold
    last modified by Scott Gerhold
  • Nand Flash, ubi On Custom t1040 board and U-BOOT

    I use SDK 2.0 to compile u-boot for my custom T1040 board. The board has MX30UF4G18AB-TI  connected to IFC_CS0 On boot it say NAND: 0 MiB, so NAND is not accesble. 1) In RCW i have ifc_MODE 0b10...
    Valeriy Urmanov
    last modified by Valeriy Urmanov
  • T2080QDS : Network issue

    Hi, I am using T2080QDS for development project. I want to transfer data to another machine. I build deployment images using Yocto and deployed images using tftp server. In boot mode I am able to ping 8.8.8.8 But ...
    Abhijit Thorat
    last modified by Abhijit Thorat
  • Does freescale git linux kernel work for T2080RDB ?

    Hello everyone,   I downloaded freescale git linux kernel from GitHub - Freescale/linux-fslc: Linux kernel source tree  and build it with this config:   make corenet64_smp_defconfig.   I al...
    ömer faruk er
    last modified by ömer faruk er
  • uboot to linux mapping

    I am new to the linux environment. Can anyone explain which device tree file will be used for linux kernel for LS1046ARDB board as there are multiple device tree files in linux folder. Am using flex installer and LSDK.
    rashmi KJ
    last modified by rashmi KJ
  • T1020 DDR Configuration

    Using QCVS document I'm able to do DDR validation. As of now I'm using T1040D4RDB as reference for making DDR changes which is in board/freescale/t104xrdb/ddr.c file. Since T1040D4RDB uses SPD for DDR configuration, I...
    Chetan Asundi
    last modified by Chetan Asundi
  • Latest yocto version(Yocto 2.7) support

    I need to compile the macsec userspace application named "hostapd" and "wpa-supplicant" for t2080rdb board. I tried to use latest yocto version 2.7 (warrior) with the meta-freescale recipes to build this application....
    Sedat Altun
    last modified by Sedat Altun
  • Using latest mainline Linux kernel for QorIQ powerpc based boards

    Hi, Is it possible to compile and deploy the latest mainline kernels from kernel.org for  powerpc QorIQ based boards ?(T2080, T4240). Or do we have to use kernels from NXP SDK?
    Sedat Altun
    last modified by Sedat Altun
  • T1022 POR cycle limit

    Hi,   On page 54 of the T1022 datasheet it states that:   "Only 300,000 POR cycles are permitted per lifetime of a device. Note that this value is based on design estimates and is preliminary."   I h...
    Bob Russell
    last modified by Bob Russell
  • T1042D4RDB SerDes Memory Mapping

    Hello,   I'm working with u-boot on T1042D4RDB, and have some question about SerDes memory mapping.   Is there a maximum physical memory region which is allocated by CPU for SerDes ? If so, is there a...
  • u-boot on custom T1024 board

    Hi,   We have developed a custom board base on the T1024. The CPU boots from an SPI memory, the SPI is programmed with the following binaries : u-boot 2016.09 binary @ offset 0x000000 of the SPI flash fsl_fman...
    Renaud De Koninck
    last modified by Renaud De Koninck
  • Codewarrior flash programming problem

    Hy,   We have a custom board with ls1046a qoriq processor on it. I would like to bring up the board by burning u-boot to the emmc with the CW flash programmer, but while running the target initialization script ...
    Kristóf Tunner
    last modified by Kristóf Tunner
  • how to get cpu temperature in t1042d4rdb

    Hi, I have QorIQ-sdk-V2.0-20160527-yocto and I can build Image for t1042d4rdb machine I want to get cpu temperature and monitor it in my application, but I cant find the temperature in its linux!   I have QorI...
    Mohsen SadeghiMoghaddam
    last modified by Mohsen SadeghiMoghaddam
  • T1042 HRESET_B Negation Problem in Power On Reset Sequence

    Hi,   I am trying to bring up a custom T1042 CPU. During power-on reset sequence via driving hard-coded cfg_rcw_src pins (driven by the FPGA), a proper HRESET timing has been observed as shown in RM Figure 4-1. ...
    Oguzhan Ardic
    last modified by Oguzhan Ardic