• Purchasing RAM that is compatible with T1042 board

    Hi,   I am trying to purchase a new RAM stick that will work the same with the T1042 board. The one i just bought is right here: https://www.amazon.com/Crucial-Single-PC4-19200-288-Pin-Memory/dp/B019FRED60?th=1...
    Jason Dejesus
    last modified by Jason Dejesus
  • How to disable some logic when the CPC is configured as SRAM on T4240

    I have configured the CPC as SRAM on the T4240 , By design, cache block consists of fast cache memory and address associative logic, this logic continuously monitoring bus transactions and perform necessary actions, i...
    同想 蔡
    last modified by 同想 蔡
  • T1042 eMMC version and device capacity

    Hi All,   We have a t1042 card with installed 8GB eMMC 4.5 and 5.0 version device. Both of them work well. What's the maximum size of eMMC t1042 supported? Can t1042 support eMMC 5.1 device? thanks.
    wengang zhu
    last modified by wengang zhu
  • Work around for t1042 DMA issues in 64 bit with ath10k WiFi

    Here is a link to the original mailing list that I posted this information to DMA issues on PowerPC64    Some background information first. I transitioned a build from 32 bit to 64 bit and discovered m...
    Jared Bents
    last modified by Jared Bents
  • IFC Guidence

    Hi! I am using t1042 and i have to interface NVRAM which is asynchronous but in IFC GPCM we can only interface synchronous memory. Please suggest me how can i interface NVRAM with IFC using GPCM. If it is not possib...
    Faiz Majeed
    last modified by Faiz Majeed
  • PORESET_B voltage value

    Hi, I would like to control the signal PORESET_B of the T2080 with a FPGA. The supply voltage of the FPGA pin is 1V5 and the supply value for PORESET_B is 1V8. On the datasheet I just found that the recommended...
    Paula García-Moreno
    last modified by Paula García-Moreno
  • HRESET_B Problem in Power On Reset Sequence

    SIr, I am using a custom made T1042 based card. I am having problem in one card because of power on sequence of the card. A CPLD is used to follow the power on sequence. As a start when I pull down the PORESET_B sign...
    Ather Shehzad
    last modified by Ather Shehzad
  • T2080 SnVDD Power Requirement

    1. Tables 6&7 of the T2080 datasheet specify SnVDD of 1.0W for all clocking scenarios. Does this figure refer to S1VDD & S2VDD combined, or 1.0W for S1VDD and 1.0W for S2VDD?   2. The T2080RDB card uses ...
    davef
    last modified by davef
  • About T1042 COP/JTAG interface connection

    Dear Responsible;   For T-series jtag connection below circuitry is recommended.  Is there any specific reason to use fictitious (theorically available but practically no) "inverted-input NOR gates" instea...
    ilhan taygurt
    last modified by ilhan taygurt
  • How to configure uboot on 2080RDB to boot a PCIe Video Card?

    We need to install debian linux for desktop on 2080RDB devkit so we need to change uboot config to boot a PCIe Video Card ( ATI) . How we can confiugure uboot?
    Roberto Innocenti
    last modified by Roberto Innocenti
  • Secure boot failed on t2080qds

    I'm working on secure boot for T2080QDS.I walked the steps,but I failed.All files come from SDK, and signed header by cst. Steps like that: set SW#6[OFF,OFF,OFF,OFF] 1.download u-boot,the file come from sdk2.0 =&g...
    Yi Li
    last modified by Yi Li
  • [T1042 Ramdisk] Kernel panic - not syncing: No working init found.  Try passing init= option to kernel. 

    Hello NXP, I want to boot with ramdisk using commands below.   tftp 1000000 uImage--4.19-r0-t1042d4rdb-64b-20200217054545.bin tftp 2000000 t1042d4rdb--4.19-r0-t1042d4rdb-64b-20200217054545.dtb tftp 3000000 asd2...
    Yusuf Altıparmak
    last modified by Yusuf Altıparmak
  • t2080 machine check investigation

    Hello all, My company is facing a problem with executing our highly accelerated testing of a handful of t2080 based systems. Background, we have delivered successfully a dozen or so of these systems that have all cyc...
    Matthew Dahl
    last modified by Matthew Dahl
  • 32-bit Physical Addressing in T1042D4RDB

    Hello,   My question is about physical addressing of T1042D4RDB. My board has 36-bit physical addressing, that means TLBs are created with 32-bit EPN and 36-bit RPN values, LAWs have 36-bit physical addressing a...
  • Displaying CPC Content

    Hello everybody,   I'm working on CCF (corenet coherency fabric) and CPC (corenet platform cache, or L3 cache) in T1042D4RDB. I studied how CCF works and uses CPC for performance about RAM I/O operations. At thi...
  • PCIe BAR Address Issue when Endpoint and RC memory is equal

    Hi, I am working on T2080 Custom board on which PCIe is connected to the upstream port of IDT PCIe switch (89PES4T4)and one of the downstream ports of the switch is connectd to Xilinx V7 FPGA (endpoint) In the vxwo...
    pushpamanjunath
    last modified by pushpamanjunath
  • qemu run with kvm enable and does not run without it

    qemu runs guest os ok with kvm enable but does not run with kvm disable. Do you guys see anything wring with these options.   Ron’s ok, I see the os initialization and I can run nbench program and measure...
    pirooz najafi
    last modified by pirooz najafi
  • U-boot Nand booting has no Fman Ucode, how to upload FMan on NAND flash ?

    Dear NXP,   With the below commands; tftp 100000 u-boot-nand-2018.09+fslgit-r0.bin nand info nand erase 0 e67c9 nand write 100000 0 $filesize   I wrote ~921 KB U-boot NAND image to NAND flash. Then change...
    Yusuf Altıparmak
    last modified by Yusuf Altıparmak
  • Converting IPV4 header to IPV6 header T4240

    Hi  NXP Community, I'm trying to convert an IPv4 header into an IPv6 header using the header manipulation table descriptor (using opcode 0x12), but I'm having some issues. I've been able to manipulate the ip sr...
    jasonforster
    last modified by jasonforster
  • DDR Single-Bit ECC QorIQ T1040

    Section 14.4.77 in T1040 Reference Manual:   In DDR_ERR_SBE register, if SBET is set to 0, then what could be expected in SBEC field? Does it count the single-bit errors? Please advice. The register description ...
    Alex Cherniakov
    last modified by Alex Cherniakov