• Corenet fabric speed

    Hi All,   In past, I think the FSB (Front Side Bus/Bus Speed) for any processor is computed against half the clock rate, so for e.g. 1.8 GHz processor with dual 32 Bit bus , both clocked at 450 Mhz. If I use the...
    last modified by Simbu
  • P4080 program RCW

    The problem is solve, please delete this request
    Andre Westerholz
    last modified by Andre Westerholz
  • How to configure P3041DS for x4 lane SerDes operation?

    What I want: to configure P3041DS for x4 lane SerDes operation on PCIe slot 7. What have I tried: * set SW2.1=1, SW2.2=1 Result: only getting x2 connection on slot 7 Question: 1. Do I need to make BSP cha...
    Peter Hua
    last modified by Peter Hua
  • Add a GMII3 Ethernet PHY on the issue P2020

    Hi All,   In relation to the past, this problem has posted a question. Try to answer back, but I just do not have the link. SGMII3 additional connection problems P2020   I need help.   Thank you. B...
    gyosun shim
    last modified by gyosun shim
  • whenever use the P2020 CPU core 1 to handle etsec interrupt ,there is packet loss

    Hi all,   I use p2020rdb-pc to design a firewall product. ETH2 and ETH1 is configured to a bridge,to do packet forward. I set the smp_affinity to use the CPU core0 for both the eth2 and eth1,I can get a throupu...
    yinzhi dong
    last modified by yinzhi dong
  • HugeTLBFS

    I'm considering using HugeTLBFS - I'm just wondering if anyone has implemented it before, and what your experience was.   And, as an additional question - has anyone ported it and used it under 32-bit linux? ...
    Paul Genua
    last modified by Paul Genua