• Booting to Linux from an SD Card/MMC for P5010

    To boot to Linux from an SD card/MMC, it is assumed that all following configuration files for booting are in the same directory under a Linux machine: RAM-based U-Boot image (u-boot.bin) Kernel image (uImage) Flat...
    Omar Cruz
    last modified by Diana Torres
  • Overcome the Challenges in Porting U-Boot and Linux® OS to QorIQ P5 Family Development Systems

    Porting the most recent version of u-boot and Linux to the newest QorIQ P5 family devices can present challenges. Enabling peripherals such as UARTs, USB, flash and using the flat device tree structure for Linux requi...
    jorge_plascencia
    last modified by Diana Torres
  • Booting P5010 from On-Chip ROM (eSDHC or eSPI)

    The on-chip ROM code does not set up any local access windows (LAWs). Access to the CCSR address space or the L2 cache does not require a LAW. It is the user’s responsibility to set up a LAW through a control wo...
    Omar Cruz
    last modified by Diana Torres
  • Hardware and Design Layout/Guidelines for P5020 DDR3 SRAM Interfaces

    Routing the DDR Memory Channel To help ensure the DDR interface is properly optimized, Freescale recommends routing the DDR memory channel in this specific order: 1. Data 2. Address/command/control 3. Clocks Note: ...
    Omar Cruz
    last modified by Diana Torres
  • P5020/P5010 Hardware Specifications/Reference Manual Specific FAQs

    According to Recommended Operating Conditions for P5020 in P5020 HW Spec, GVDD = 1.35V/1.5V while XVDD = 1.5V/1.8V. What power should I use for the XVDD? 1.5V? 1.8V? According to P4080 specs, XVDD = GVDD. Does this me...
    Omar Cruz
    last modified by Omar Cruz
  • P5020/P5010 COP/JTAG Specific FAQs

    The JTAG IDCODE for P5010 is 0x0020c01d. What's the IDCODE for the P5010? Below are the JTAG IDCODES for P5010 and P5020: P5010: 0x0020_D_01D P5020: 0x0020_C_01D   For P5020, COP header has COP_CHKSTP_OUT a...
    Omar Cruz
    last modified by Omar Cruz
  • P5020/P5010 Device Ratings Specific FAQs

    I assume that 50mV specification for P5020 includes all kinds of voltage variations, such as DC regulation, steady-state ripple and transients. Is this correct? I would like to know the maximum current step and slew r...
    Omar Cruz
    last modified by Omar Cruz
  • Booting to Linux from an SD Card/MMC for P4080

    To boot to Linux from an SD card/MMC, it is assumed that all following configuration files for booting are in the same directory under a Linux machine: RAM-based U-Boot image (u-boot.bin) Kernel image (uImage) Flat...
    Omar Cruz
    last modified by Diana Torres
  • Hardware and Design Layout/Guidelines for P4040 DDR3 SRAM Interfaces

    Routing the DDR Memory Channel To help ensure the DDR interface is properly optimized, Freescale recommends routing the DDR memory channel in this specific order: 1. Data 2. Address/command/control 3. Clocks Note: ...
    Omar Cruz
    last modified by Diana Torres
  • Booting P4080 from On-Chip ROM (eSDHC or eSPI)

    The on-chip ROM code does not set up any local access windows (LAWs). Access to the CCSR address space or the L2 cache does not require a LAW. It is the user’s responsibility to set up a LAW through a control wo...
    Omar Cruz
    last modified by Diana Torres
  • P4040 Clocking Specific FAQs

    For P4040, does DDRCLK and PCIe (SerDes) ref clock support a spread spectrum reference? DDRCLK and PCIe (SerDes) ref clock support spread spectrum. Please note that since SGMII doesn't support spread spectrum, if SGM...
    Omar Cruz
    last modified by Omar Cruz
  • P4040 Reset Configuration Specific FAQs

    Do we have an internal pull up on LA20 pin in P4040E? According to hardware spec for P4040, LA20 pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in t...
    Omar Cruz
    last modified by Omar Cruz
  • P4040 eSPI/FLASH Specific FAQs

    Can the P4040 eSPI controller address 4-byte (32-bit) addressable EEPROMs in any situation? Yes, eSPI controller addresses 4-byte addressable EEPROMs in any situation. For P4040, is it possible to boot from a 4-byt...
    Omar Cruz
    last modified by Omar Cruz
  • P4040 Ethernet Specific FAQs

    How can I ensure that Ethernet flow control is turned on through the register setting in P4040? Please try the below steps to enable Ethernet flow control: 1) Set MACCFG1[Rx_Flow] && MACCFG1[Tx_Flow] to 1 2) ...
    Omar Cruz
    last modified by Omar Cruz
  • P4040 Software Tools - CodeWarrior Specific FAQs

    Usually, when I turn on the option of "reset target on launch" CW resets CPU again while connecting to CPU. With P4040, CodeWarrior (CW) does not connect to CPU when the option is on, only when I disable the option, C...
    Omar Cruz
    last modified by Omar Cruz
  • P4080 Hardware Specifications/Reference Manual Specific FAQs

    I don’t use SDHC, and we use SPI at 2.5V (CVDD=2.5V). In this case for P4080 unused SDHC pins are pulled up to 2.5V. If I want to maintain compatibility with P4040, what happens when unused SDHC pins (SDHC_DATA ...
    Omar Cruz
    last modified by Omar Cruz
  • P4080 DDR Specific FAQs

    What is requirement for the voltage ripple of DDR3 controller MVref? The nominal value of MVref is 1.5V. 1%, +/- 7.5mV is the tolerance value for MVref (ripple range). Can you please explain the RDRVR resistance fo...
    Omar Cruz
    last modified by Omar Cruz
  • P4080 USB Specific FAQs

    If I don’t use the USB interface in the 4080, can I leave USBx_VDD_3P3 and USBx_VDD_1P0 pins not connected? In P4040 they are reserve with note do not connect. Can they be connected to 3.3V and 1.0V respectively...
    Omar Cruz
    last modified by Omar Cruz
  • P4080 Ethernet Specific FAQs

    The SGMII SerDes of the 4080 can operate at either 1.25G or 2.5G. Is there a register to configure this or it just depends on the clock multipliers of the SerDes PLL? As long as you select the RCW settings for SRDS_PR...
    Omar Cruz
    last modified by Omar Cruz
  • Hardware and Design Layout/Guidelines for P3041 DDR3 SRAM Interfaces

    Routing the DDR Memory Channel To help ensure the DDR interface is properly optimized, Freescale recommends routing the DDR memory channel in this specific order: 1. Data 2. Address/command/control 3. Clocks Note: ...
    Omar Cruz
    last modified by Diana Torres