• CPLD update using JTAG in P1022 processor

    We are trying to update (lattice) CPLD in our P1022 board using JTAG . In this mode Processor GPIO's are configured as TMS, TCK, TDi, TDO respectively and Cpld is updated using vme file. The toggling of TCK pin(GPIO)...
    Hemwant Rawat
    last modified by Hemwant Rawat
  • Design files for p1020rdb-pa

    Where might we locate design files (layout, schematic, BOM, BSP, etc.) for the P1020RDB-PA?   Please note, that this is REV. A of this board. All of the design files I can seem to locate are for more recent revs...
    last modified by sharper
  • P1022 BSDL

    Is there a BSDL file for the P1022 QorIQ Processor?  I am reviewing Boundary Scan testability on a board and need a BSDL file for the BScan tool.
    Dennis Sauer
    last modified by Dennis Sauer
  • is possible to use MT29F8G08ABACAWP-IT with P1020/P1011?

    Hello, I'd like to know if is possible to use MT29F8G08ABACAWP-IT with P1020/P1011? If yes, how can I add support for that in u-boot and Linux kernel based on SDK 2.0.   Thanks Leandro Schmitz
    Leandro Schmitz
    last modified by Leandro Schmitz
  • how can i use 4K-page nand (MT29F8G08ABACAWP) in P1020/P1011

    hello experts CPU is P1020/P1011  and a borad was  used a few years without problems kernel and u-boot are from SDK 1.8 this time  i have to install 1GB nand  so i  plan to&#...
    hyoungki kim
    last modified by hyoungki kim
  • TDM on P1020 within vxWorks

    To anybody that has experience with P1020 and TDM,     I have a question a question about TDM on P1020 I have the TDM working just fine on within Linux and trying to make it it work within vxWorks I have ...
    Naum Grutman
    last modified by Naum Grutman
  • P1020RDB-PD  TDM  tests and issues

    In reference to the other thread:   TDM Driver Working in Internal Loopback mode During Validation    The document within it  TDM Driver Working in Internal Loopback mode During Validation.pdf d...
    Naum Grutman
    last modified by Naum Grutman
  • eLBC memory map

    Can I configure eLBC memory map of P1020 as below in a same LAW:   Start address: 0x0_F0000000  ----NOR Flash start address (256MB size) End address: 0x0_FFFFFFFF ----NOR Flash end address Start address: ...
    udaya kumar
    last modified by udaya kumar
  • P1010 reports "Data Cache Parity Error"

    CPU:P1010 OS: linux-3.8.13 Error information output from linux as below: kernel-2: Machine check in kernel mode. kernel-2: Caused by (from MCSR=10000000): Data Cache Parity Error kernel-2:Oops: Machine check, sig...
    Qingshan Li
    last modified by Qingshan Li
  • The role of the diode of the VBUSCLMP pin on P1010

    In the P1010RDB manual,a diode is connected in parallel with the VBUSCLMP pin,and what is the role of this diode?       Thanks.
    露 唐
    last modified by 露 唐
  • Deffered callback manager

    Hi to all I develop Deffered callback manager at P1010. DCM is designed to handle low priority task queues. Deffered callback manager is started by asynchronous low-priority interrupt (PRIORITY_1 = 0x10...
    andy tsybezoff
    last modified by andy tsybezoff
  • DDR3 auto calibration error and reserved register change in running time

    hi all      i have a custom board use P1013 CPU with four discrete DDR3 chips. the board can run vxworks OS normally, but every about 4-10 hours the board will crash. When board crash happen i use JTAG...
    zhao lingjun
    last modified by zhao lingjun
  • Interrupt priority on the Linux P1020 - How to set it up?

    Hello,   I'm writing a linux kernel driver in order to control the 6 IRQs on the P1020.   My approach is to configure those IRqs in the device tree, to map them using irq_of_parse_and_map, to request them ...
    last modified by alfonsokame
  • TSEC rx DMA putting in wrong spot?

    I'm writing drivers for the TSEC.  I'm able to transmit.  I'm trying working on a bug while receiving. While setting up my Receive Buffer descriptors, I set the buffer pointer to their corresponding arrays...
    Zachary Wilcox
    last modified by Zachary Wilcox
  • IOMMU disable in kernel

    Hi, We have P2041RDB with DDC 1553 (Muxbus) PCIe card inside. In order to enable DMA mode of the card, the vendor requests to disable IOMMU support in the Linux kernel. The question is, what the impact of t...
    Eli Mintz
    last modified by Eli Mintz
  • Changing IVPR on the P1021 causes Program Interrupt Exception

    I'm attempting to change the IVPR.  I'm doing this by setting MSR[EE] = 0, setting the IVPR register, some other initialize stuff, then setting MSR[EE]  = 1. I then get a program interrupt exception and jump...
    Zachary Wilcox
    last modified by Zachary Wilcox
  • Reading where CCSRBAR points to on P1021

    Is there a register where you can read where the CCSRBAR address starts at on the P1021   Something like   mfspr CCSR, r1   Where R1 would know have the contents of where the CCSRBAR points to?  ...
    Zachary Wilcox
    last modified by Zachary Wilcox
  • P1021 cache-inhibited?

    I'm working with the P1021.  The Reference Manual states that if CCSR space is used, then it should be marked as cache-inhibited and guard. How do I mark this address space, or any other address space as cache...
    Zachary Wilcox
    last modified by Zachary Wilcox
  • P2040: Issue with MMC/SD card in kernel

    Hi, In my custom board, based on P2041rdb, SD/MMC card is throwing following error while linux is booting up,   mmc0: new high speed SDHC card at address b368 mmcblk0: mmc0:b368 SDC 7.34 GiB mmcblk0: error -11...
    gourav jain
    last modified by gourav jain
  • Can't see any i2c device in /dev/ directory (like dev/i2c-0 and dev/i2c-1)

    Dear all,   I have loaded the compiled QorIQ-SDK-V1.2-20120614-yocto linux kernel module on p1021 (2C, 900M) based board and get into linux prompt. Then I try to let it support for i2c interface.   I ha...
    Lin Hsin Han
    last modified by Lin Hsin Han