• how  to   include the NTP  server  moudle?

    hi       my demo board is  P2020DS ,  i  use the sdk1.6.   I want use  the p2020ds  as  NTP  server ,  how  to   include the NTP...
    xiaonan peng
    last modified by xiaonan peng
  • ubifsmount p2020ds-rootfs           error

    my demo board is  P2020DS ,  i  use the sdk1.6,  mount  one  mtd  , ubifsmount p2020ds-rootfs               ...
    xiaonan peng
    last modified by xiaonan peng
  • T1023 boot problem

    Hi! I made a commercial board using the T1023NXE7MQA, but when power-on, it does not work. The power-on sequence also works as recommended, and power-on reset configuration and RCW are also normal. (Check with scope) ...
    jaehwan sun
    last modified by jaehwan sun
  • Gianfar skb errors

    Hello,   CPU:  e300c1, MPC8343A, Rev: 3.0    I am experience kernel panics using Kernel 4.19.87 related to, what appears to be, socket buffer corruption. A few different crashes occur upon traffi...
    Richard Roth
    last modified by Richard Roth
  • How to configure DDR SDRAM controller in MPC8358E processor?

    Hi Good evening,   I am working on mpc8358 processor, I am using DDR SDRAM memory, I need some reference documents for configuring the controller. I have an AN3399 document but it is referring to DDR2. please pr...
    venkat d
    last modified by venkat d
  • P2020DS  sdk1.6   ERROR: QA Issue: non debug package contains .debug directory:

    HI      When   I  change  \linux-qoriq-sdk\3.12-r0\git\arch\powerpc\boot\dts\p2020ds.dtsi  or recover the same.  then  I  comepile again  .  ...
    xiaonan peng
    last modified by xiaonan peng
  • T1042 RCW source pins

    Hello,              We have multiple boards with a T1042 processor. So this problem is in only one card. Card specific problem.       ...
    ankur kumar
    last modified by ankur kumar
  • Access Local Bus simultaneously

    Hi,   I'm using MPC8569, with a NAND flash and DSP connected to Local Bus using different chip select. If MPC8569 and DSP exchanging data, while another task recording logs to NAND flash periodically, we found t...
    Jia Guo
    created by Jia Guo
  • e5500 core document

    I'm looking at the e5500 core reference manual for the definitions of some bits but there are no definitions of bits in the e5500 Core Reference Manual and some bits of some registers are also not defined.   &#...
    unknown issuee
    last modified by unknown issuee
  • P2020 UBOOT ADD  UBIFS  macro  cause problem

    hi       my demo board is  P2020DS ,  i  use the sdk1.2,  Add  saome macro in the p2020ds.h of uboot such as bellow   #define CONFIG_MTD #define CONFIG_MTD_DEVI...
    xiaonan peng
    last modified by xiaonan peng
  • MPC5748G multi-core operation problem

    When using Lauterbach to debug multi-core applications (first use In target reset, then run), both the z4_0 and z4_1 cores can run normally; but after removing the debugger, only z4_0 can run, while the z4_1 core cann...
    zhou wei
    last modified by zhou wei
  • Programming the MPC8360

    Good Day, We are migrating from the MPC8260 Processor to the MPC8360. On the MPC8260 we pull the RSTCONF_ pin low to place the the Processor in defualt config to allow configuration.    Is there in Pin/ si...
    Hendrik Bence
    last modified by Hendrik Bence
  • Four differences between QorIQ SDK V1.9

    Question 1, what is the difference between the following four?   1. Cache: QorIQ SDK V1.9 PPCE500V2 CACHE 2. Image: QorIQ SDK V1.9 PPCE500V2 IMAGE 3. Source: QorIQ SDK V1.9 SOURCE 4. Virtual Host Enviroment: Qor...
    xiao cheng
    last modified by xiao cheng
  • Max DDR2 clock of MPC8349 with 533 MHz CSB?

    Hi,   MPC8349EA Hardware Specifications Rev 13 says in note 4 of Table 66 that "AJF marked parts support DDR1 and DDR2 data rate up to 333 MHz (at a CSB of 333 MHz)." However, Table 57 says that AJF devices (i.e...
    Etienne Alepins
    last modified by Etienne Alepins
  • CPO vs automatic calibration for DDR2

    The CPO parameter in the TIMING_CFG_2 register indicates that this parameter is an override and the reference manual also seems to indicate that that this parameter (CAS-to-preamble) is calibrated automatically at POR...
    Dallas Clow
    last modified by Dallas Clow
  • sdram data swapping

    I would like to know MPC885  databus(31:0) connectivity   to SDRAM  MT48LC2M32. Shall we need to connect D0 of MPC885 to D0 of SDRAM or D0 of mpc885 to d31 of SDRAM. As mpc885 is in big-endian...
    last modified by padmayarraguntla
  • NFS boot fails P4080DS

    Hi, we're trying to setup NFS boot for P4080DS with host as Ubuntu 14. we've followed Yocto NFS & TFTP boot document. after u-boot we've booted through   =>tftp 1000000 uImage =>tftp c00000...
    appalanaidu g
    last modified by appalanaidu g
  • DDR DRAM mode register address bits

    Are the bank address bits of the mode register settings (two msb's) of each field in DDR_SDRAM_MODE and DDR_SDRAM_MODE_2 used by the DDR controller at initialization or are they ignored?  There is a separate fiel...
    Dallas Clow
    last modified by Dallas Clow
  • ODT and additive latency

    The ODT_WR_CFG parameter of the CSn_CONFIG register indicates that write latency plus additive latency must be at least 3 to use ODT.  Our application uses an MPC8610 with 64-bit DDR2 w/ECC running at 200 MHz (DD...
    Dallas Clow
    last modified by Dallas Clow
  • uboot will be crash after P2020 Enable ECC

    Hello everyone,   I am using P2020 with 2GB of DDR3 (MT41K256M16 – 32 Meg x 16 x 8 banks)memory, uboot hangs(Crash) after enabling ECC (Address: 2000h base + 110h offset = 2110h, bit 2 = 1);   W...
    xiao cheng
    last modified by xiao cheng