• Programming the MPC8360

    Good Day, We are migrating from the MPC8260 Processor to the MPC8360. On the MPC8260 we pull the RSTCONF_ pin low to place the the Processor in defualt config to allow configuration.    Is there in Pin/ si...
    Hendrik Bence
    last modified by Hendrik Bence
  • Four differences between QorIQ SDK V1.9

    Question 1, what is the difference between the following four?   1. Cache: QorIQ SDK V1.9 PPCE500V2 CACHE 2. Image: QorIQ SDK V1.9 PPCE500V2 IMAGE 3. Source: QorIQ SDK V1.9 SOURCE 4. Virtual Host Enviroment: Qor...
    xiao cheng
    last modified by xiao cheng
  • Max DDR2 clock of MPC8349 with 533 MHz CSB?

    Hi,   MPC8349EA Hardware Specifications Rev 13 says in note 4 of Table 66 that "AJF marked parts support DDR1 and DDR2 data rate up to 333 MHz (at a CSB of 333 MHz)." However, Table 57 says that AJF devices (i.e...
    Etienne Alepins
    last modified by Etienne Alepins
  • CPO vs automatic calibration for DDR2

    The CPO parameter in the TIMING_CFG_2 register indicates that this parameter is an override and the reference manual also seems to indicate that that this parameter (CAS-to-preamble) is calibrated automatically at POR...
    Dallas Clow
    last modified by Dallas Clow
  • sdram data swapping

    I would like to know MPC885  databus(31:0) connectivity   to SDRAM  MT48LC2M32. Shall we need to connect D0 of MPC885 to D0 of SDRAM or D0 of mpc885 to d31 of SDRAM. As mpc885 is in big-endian...
    padmayarraguntla
    last modified by padmayarraguntla
  • NFS boot fails P4080DS

    Hi, we're trying to setup NFS boot for P4080DS with host as Ubuntu 14. we've followed Yocto NFS & TFTP boot document. after u-boot we've booted through   =>tftp 1000000 uImage =>tftp c00000...
    appalanaidu g
    last modified by appalanaidu g
  • DDR DRAM mode register address bits

    Are the bank address bits of the mode register settings (two msb's) of each field in DDR_SDRAM_MODE and DDR_SDRAM_MODE_2 used by the DDR controller at initialization or are they ignored?  There is a separate fiel...
    Dallas Clow
    last modified by Dallas Clow
  • ODT and additive latency

    The ODT_WR_CFG parameter of the CSn_CONFIG register indicates that write latency plus additive latency must be at least 3 to use ODT.  Our application uses an MPC8610 with 64-bit DDR2 w/ECC running at 200 MHz (DD...
    Dallas Clow
    last modified by Dallas Clow
  • uboot will be crash after P2020 Enable ECC

    Hello everyone,   I am using P2020 with 2GB of DDR3 (MT41K256M16 – 32 Meg x 16 x 8 banks)memory, uboot hangs(Crash) after enabling ECC (Address: 2000h base + 110h offset = 2110h, bit 2 = 1);   W...
    xiao cheng
    last modified by xiao cheng
  • P2020 L2 cache seems to slow down execution

    Hello,   I have been investigating a CPU stall issue with my project. I realized that the number of instruction completed in a second (number retreived thanks to PMCs) is higher when I disable the L2 cache. ...
    Alexy Torres
    last modified by Alexy Torres
  • MPC5744 ADC 采样通道第一次切换时结果偏小

    大家好,    我们电机控制系统是低端3电阻采样,使用MPC5744,CTU控制一个控制周期采样其中两相电流,在扇区切换,需要切换ADC通道的时候,出现了一个问题,切换的这个通道采样值偏低,导致q轴电流出现凸起波动,第二个控制周期采样的相电流和后面采样的相电流差值就比较均匀。如下图所示第一行曲线是实际q轴电流,第二行曲线是采样的两个电流AD值,第三个是扇区,q轴电流每一个凸起地方都是ADC通道切换地方,最后一...
    xaing.wang@tuopu.com
    last modified by xaing.wang@tuopu.com
  • T4240 Memory problems

    T4240rm states that each channel has a maximum of 64GB, but it is later explained that each slice supports a maximum of 4GB, which is inconsistent? How much memory capacity can this chip support? What are the restrict...
    克祥 黄
    last modified by 克祥 黄
  • MPC8280 boot failure

    Hello, We have produced a batch of MPC8280 prototypes. After burning the boot, there are several prototype serial port printing information as follows: The information in the red box is redundant abnormal informat...
    Chen Kun
    last modified by Chen Kun
  • Flashing instructions for MPC8315E-RDBA board

    Hi,   Can anybody explain how to flash u-boot on NOR flash of MPC8315E-RDBA board? I'm using CodeWarrior 8.8 + patch 8.8.6 and CodeWarrior TAP. I tried all possible combination of CW flasher with no visible re...
    Eduard Bartosh
    last modified by Eduard Bartosh
  • Accessing SATA

    Hi All  I have Processor T1042 ,where I want to access Sata controller .  What all things I need to take care before accessing the registers of SATA .
    utkarsh rawat
    last modified by utkarsh rawat
  • RTOS for PowerQUICC II (MPC82xx)

    Hello. The title explains it. Is there an RTOS for PowerQUICC II (MPC82xx)? Thanks in advance.
    Koray Erer
    last modified by Koray Erer
  • Maximum speed (Frequency) of the MPC8548 COP interface

    Hi, Need information of maximum speed (Frequency) of the MPC8548 COP interface  to ensure signal integrity when designing with MPC8548 device on board. Is it same as the JTAG clock frequency: 33MHz? Thanks Louis
    Louis Sankoorikal
    last modified by Louis Sankoorikal
  • The difference between LWE_B[0] and LWE_B[1] of enhanced local bus controller

    As described in P2020RM about enhanced local bus controller (eLBC): Two byte-write-enable signals (LWE_B[0:1]). Asserted/Negated-For GPCM operation, LWE_B[ 0:1] assert for each byte lane enabled for writing. So my que...
    guobin lu
    last modified by guobin lu
  • Codewarrior Ethernet TAP Clarifcation

    Hi. We are developing a product using MPC8349E. We are planning to buy CWH-CTP-BASE-HE along with CWH-CTP-COP-YE. I have the following clarifications on the same.   1. Whether the above part number if purchased...
    Harish Kumar
    last modified by Harish Kumar
  • Cache Perfromance E300 Core MPC8349E

    We want to analyze the cache misses and DRAM access for MPC8349E powered by e300 Core. Basically we have a flight control algorithm, we need to measure the cache misses each time we execute the controller for(;;) { ...
    Micheal Saleab
    last modified by Micheal Saleab