• PowerQUICC Wiki

    This section is essentially created to help all PowerQUICC Processor users ranging from customers to designers to help provide the best solution to the most frequently encountered questions related to PowerQUICC Proce...
    -nilda
    last modified by Diana Torres
  • IMG_20131126_190556.jpg

    Freescale-PC PCI express connector.
    aleksandr Muraviov
    last modified by aleksandr Muraviov
  • MPC8306: Low-Power PowerQUICC II Pro Processor

    Table of Contents  Table of Contents Product Information on Freescale.com Frequently Asked Questions (FAQ) Other Resources   Product Information on Freescale.com  MPC8306 Product S...
    -nilda
    last modified by -nilda
  • MPC8567/MPC8568 Hardware Specifications/Reference Manual Specific FAQs

    For MPC8568, local bus has pin LAD [0:31] and LA [27:31]. LAD [0:31] is named as Muxed Data/ Address bus while LA [27:31] as address bus. Can LAD [27:31] be used as address bus in muxed mode using LALE signal? Yes, y...
    Omar Cruz
    last modified by Omar Cruz
  • MPC8543/MPC8545/MPC8547/MPC8548 Hardware Specifications/Reference Manual Specific FAQs

    Does this output signal really need the pull up? Yes, IRQ_REQ output signal requires 2-10K ohm pull-up According to the section 20.10 of 8548EEC, SD_REF_CLK/SD_REF_CLK_B must be connected to GND if not used. Is thi...
    Omar Cruz
    last modified by Omar Cruz
  • MPC8543/MPC8545/MPC8547/MPC8548 GPIO Specific FAQs

    Can the 8543 support the 16bit FIFO by combining the eTSEC1 pins with the GPIO pins that would otherwise be assigned to eTSEC2 in MPC8548? It is recommended for the unused I/O pins (such as the MECC [0:7]) to be pull...
    Omar Cruz
    last modified by Omar Cruz
  • MPC8541 Power Management Specific FAQs

    I would like to know if output signals of blocks which are not clocked during sleep mode are driven or not. For example, are eTSEC2 RGMII signals driven during sleep mode? Yes, they would be driven but there would be...
    Omar Cruz
    last modified by Omar Cruz
  • MPC8541 PCIe Specific FAQs

    Does the PCIe controller go to D3 hot state automatically if the user does not configure any registers? Should the external device be in D3 hot state explicitly before MPC8541 goes to sleep mode? PCIe controller will...
    Omar Cruz
    last modified by Omar Cruz
  • MPC8541 Ethernet (eTSEC) Specific FAQs

    Can you please confirm that the MPC8541 ethernet input clock is actually 2 clocks: one for each eTSEC, with name TSECn_GTX_CLK125/GPIOm? The MPC8541 ballmap spreadsheet only shows one gtx_clk125 pin (like the 8536), b...
    Omar Cruz
    last modified by Omar Cruz
  • MPC8541 eSDHC Specific FAQs

    The SD card spec requires SD clock to supply for at least 74 clock cycles. On the other hand, the eSDHC controller in MPC8541 supplies about 13 SD clock cycles (with 180 degrees phase shift) at power up. Will SD card ...
    Omar Cruz
    last modified by Omar Cruz
  • MPC8541 DDR Specific FAQs

    For MPC8541, when I am using a DDR controller with a 64-bit interface with a 32-bit memory sub system, which lanes should I use? When a 64-bit DDR interface is configured in a 32-bit data bus width, lanes [0:3] (MDQ ...
    Omar Cruz
    last modified by Omar Cruz
  • MPC8541 Clocking Specific FAQs

    For MPC8541, what is the maximum bit rate clock for SSI? Is it really 12.285MHz or can it be run up to platform clock / 8? Maximum bit rate clock for SSI is as per hardware spec i.e. 12.285MHz. This is the maximum sp...
    Omar Cruz
    last modified by Omar Cruz
  • MPC8541 Hardware Specifications/Reference Manual Specific FAQs

    Can MPC8541 GPIO signals drive LEDs directly? What is the output current requirement (Iol / Ioh) for GPIO signals? Yes, MPC8541 GPIO signals can drive LEDs directly. When GPIO is driven HIGH, to maintain a voltage of...
    Omar Cruz
    last modified by Omar Cruz
  • MPC8536 Hardware Specifications/Reference Manual Specific FAQs

    Note 2 of table 13 in MPC6536 hardware spec mentions: "Peak-to-peak noise on MVREFn may not exceed +/- 1% of the DC value." What is "the DC value"? The DC value is the GVdd value. Do you have any typical estimated ...
    Omar Cruz
    last modified by Omar Cruz
  • MPC8536 eSDHC Specific FAQs

    MPC8536 Hardware spec states that either SDHC_CD, or SDHC_DAT3 can be used for card detection. Do you have to set the bit PROCTL[D3CD] specifically, if you want to use the DAT[3] method? This, plus adding the pull-dow...
    Omar Cruz
    last modified by Omar Cruz
  • MPC8536 DDR Specific FAQs

    Is it correct that TIMING_CFG_5[RODT_ON] and TIMING_CFG_5[RODT_OFF] do not affect internal ODT circuit for MPC8536? These values are always set in u-boot for our DDR3 based boards (e.g. P2020DS, MPC8569MDS). However e...
    Omar Cruz
    last modified by Omar Cruz
  • MPC8536 Clocking Specific FAQs

    MPC8536 PCI controller can get clock from SYSCLK (synchronous) or from PCICLK (PCI asynchronous mode). If PCI is configured as PCI asynchronous mode, a valid clock must be provided on pin PCICLK, otherwise the process...
    Omar Cruz
    last modified by Omar Cruz
  • MPC8535 Hardware Specifications/Reference Manual Specific FAQs

    Note 2 of table 13 in MPC8535 hardware spec mentions: "Peak-to-peak noise on MVREFn may not exceed +/- 1% of the DC value." What is "the DC value"? The DC value is the GVdd value. Do you have any typical estimated n...
    Omar Cruz
    last modified by Omar Cruz
  • MPC8535 eSDHC Specific FAQs

    MPC8535 Hardware spec states that either SDHC_CD, or SDHC_DAT3 can be used for card detection. Do you have to set the bit PROCTL[D3CD] specifically, if you want to use the DAT[3] method? This, plus adding the pull-dow...
    Omar Cruz
    last modified by Omar Cruz
  • MPC8535 DDR Specific FAQs

    Is it correct that TIMING_CFG_5[RODT_ON] and TIMING_CFG_5[RODT_OFF] do not affect internal ODT circuit for MPC8535? These values are always set in u-boot for our DDR3 based boards (e.g. P2020DS, MPC8569MDS). However e...
    Omar Cruz
    last modified by Omar Cruz