Adrian Stoica

i.MX RT memory validation

Blog Post created by Adrian Stoica Employee on Dec 6, 2019

Memory validation extends Peripherals tool with the capability to validate different types of memories. For now, it supports RT10xx CPUs family with SEMC/SDRAM and FlexSPI/NOR (starting with MCUXpresso v11.1.0/Config tools v7) devices. 

 

The SEMC is a multi-standard memory controller optimized for both high-performance and low pin-count. It can support multiple external memories in the same application with shared address and data pins. The interface supported includes SDRAM.

 

FlexSPI is a flexible SPI (Serial Peripheral Interface) host controller which supports two SPI channels and up to 4 external devices. Each channel supports Single/Dual/Quad/ Octal mode data transfer (1/2/4/8 bidirectional data lines).

 

For developing hardware with SDRAM memory connected to SEMC controller or with NOR memory connected to FlexSPI controller, the validation of memories settings can be done with the new introduced validation tool. The tool is available for SEMC and FLEXSPI peripherals and can be used after selecting the SEMC or FLEXSPI peripheral from the list in the Peripherals view.

 

 

Note:

  • This document assumes the use of MCUXpresso IDE v11.0.0 (or later).
  • An MCUXpresso SDK for RT10xx CPUs family will also be required
  • This must be “SDK Version: 2.5.0 (released 2019-02-25)” or later – which can be obtained from https://mcuxpresso.nxp.com
  • Installation of Python 2.7 is required (Install the latest of Python 2.7 version available on  https://www.python.org/downloads). If you see connection errors, make sure arm-none-eabi-gdb-py (can be found in \MCUXpressoIDE_11.1.0\ide\plugins\com.nxp.mcuxpresso.tools.win32\tools\bin\) is starting without error. Also, on Windows it is possible that python27.dll to be required and must be placed in Python27 installation folder. 
  • Once the SDK is imported into MCUXpresso IDE and a project including SEMC or FlexSPI driver is created, the settings can be tuned and validated following the next steps

 

Example below is for SEMC with SDRAM:

 

  1. Select the project and open the Peripherals tool 
  2. Select the SEMC component
  3. Configure the SDRAM parameters using the UI
  4. Click on Validation View icon to open SEMC Validation tool view
  5. From Validation view can be selected validation scenarios and tests. Available tests are DMA,
    Write-Read-Compare, Walking Ones, Walking Zeros. Also Stress test scenario (starting with MCUXpresso v11.1.0/Config tools v7) is available for SDRAM.
    DMA test will transfer data from a source address to a destination address in SDRAM. The size of the data transferred is configurable. The source region is filled with a repeating pattern. After DMA finished the transfer, the test is reading back the data from the destination and compares it with the source data. The test fails at the first mismatch found.
    Write-Read-Compare test checks SDRAM reads versus writes. Sequentially writes into a SDRAM area a pattern, until area is fully covered. Then reads back from the same SDRAM area and compare with what has been written. User can set the start and size of SDRAM area and pattern to be used. The test fails after the first identified memory mismatch.
    Walking Ones test writes a bit pattern that gradually sets [to 1] bits from LSB to MSB. Each byte is written multiple times depending on the selected access size, until each of the contained bits gets set, while the other ones are cleared. For each bit pattern, a write/read/compare sequence is performed. The test is repeated for each of the access size selected using the corresponding access size.
    Walking Zeros test writes a bit pattern that gradually clears [to 0] bits from LSB to MSB. Each byte is written multiple times depending on the selected access size, until each of the contained bits gets set, while the other ones are cleared. For each bit pattern, a write/read/compare sequence is performed. The test is repeated for each of the access size selected using the corresponding access size.
    Stress test is a suite of tests meant to verify the performance and stability of the memory in a non-OS environment.
  6. To set the test parameters and the number of repetitions go to Choose Tests tab
  7. Once the test parameters are set and the scenario is selected, validation can be started by clicking on Start Validation button
  8. Status of the test will be displayed in Test Results view
  9. In Logs view Simple or Real time log can be displayed for each test 
  10. For SDRAM once the validation tests succeeded, there are two options to set the target with the new SDRAM settings
    1. C code generation. Necessary C code for setting the SDRAM is generated in peripherals.c/.h files and will be deployed into the project by pressing Update Code button. Also, a preview of the code is available in Code Preview tab
    2. Create a DCD C array or binary with the SDRAM settings by using the Apply to DCD option.
      First is necessary that the SEMC component mode to the switched to DCD. This way only DCD component will be updated with the SEMC settings and not the peripherals.c/.h files. 
      1. After pressing Apply to DCD button, open DCD tool to view the SDRAM initialization 
      2. SDRAM configuration generated into DCD is supposed to be used to update the existing configuration. We are not expected the board to boot with this configuration alone.
  11. Once the validation process is done and the SDRAM settings were applied using one of the above options, project can be rebuilt with the validated SDRAM settings

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