• LPC55S69 : what is NOP for flash memory ?

    Hi !   Unfortunately flash memory can be written by 512 bytes chunks only. But I need to sabe small 16-128 bytes chunks and I can see I can read modify and write the same page several times.   LPC55S69 fl...
    Eugene Hiihtaja
    last modified by Eugene Hiihtaja
  • LPC55s69 : hardfault in FFR region

    Hi !   I have environment based on SDK example free_rtos_mpu_s/ns couple.   I have applied  S-User ( NS-User by default) for last 32KB flash block : 0x98000 - 0x9FFFF where FFR region located also. &#...
    Eugene Hiihtaja
    created by Eugene Hiihtaja
  • How to fix LPC55Sxx AHB Read HardFault Error

    Recently I have several customers experience HardFault error when perform AHB FLASH memory read on LPC55S69. If a FLASH sector has never been programed after mass erase, performing AHB reads of the FLASH memory conten...
    ZhangJennie
    last modified by ZhangJennie
  • LPC55S69-EVK USB0 ISP mode not working

    Hi,   I'm experimenting with the LPC55S69-EVK and was now testing the ISP functionality. I've now noticed that the USB ISP mode only works when using USB1 and not on USB0.   Pressing button ISP...
    dingelen
    last modified by dingelen
  • LPC55S69 Secure Boot Failing

    Hello, I am trying to configure a LPC55S69-EVK to demonstrate the secure bootloader and secure update via SB2 loading and I'm not able to get anything to boot when the secure boot option is enabled (boot signed images...
  • LPC55S69 : erased flash state

    Hello ! 1. Do I understand right  and FLASH API is designed for be called from secure side only ? #define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x130010f0U) #define VERSION1_FLASH_API_TREE BOOTLOA...
    Eugene Hiihtaja
    last modified by Eugene Hiihtaja
  • LPC55S69: reinit after power-down mode

    Hi !   Looks like after power-down mode  almost all peripherals should be reinitialized.   " It is the responsibility of the customer application to re-configure all modules in the power domain core ...
    Eugene Hiihtaja
    last modified by Eugene Hiihtaja
  • LPC55S69: USB_SRAM clean up over reboot ?

    Hi ! I try to see if USB_SRAM at ox50100000 can be used for keep some data over reboot. And it seems to me it is wiped by 0x00 by ROM code every reboot even ISP USB flashing is not used. SRAM4 area at 0x30040000 is...
    Eugene Hiihtaja
    last modified by Eugene Hiihtaja
  • LPC55S69 : recover after Flash Error

    Hi !   During flash erase/program operation error can happens and it seems to me it is not recoverable. Even reading of this area of memory cause Hardfault. Only erasing of whole flash can suppress it.   ...
    Eugene Hiihtaja
    last modified by Eugene Hiihtaja
  • LPC55S69 : minimal PRINCE write chunk

    Hello !   I can see SDK example about encryption/description on fly to flash memory by using PRINCE engine.   /* Loading data into the PRINCE - controlled flash area. Note, that following conditions must ...
    Eugene Hiihtaja
    created by Eugene Hiihtaja
  • LPC55S69 : FreeRTOS with MPU example

    Hi !   You have provide very good example of Freertos for LPC55S69 what is run in nonsecure world and task can call secure world.   But it is not so clear if if privided example can be transformed to case...
    Eugene Hiihtaja
    created by Eugene Hiihtaja
  • LPC55S69 : flash_iap example on A2 board

    Hello !   Does flash_iap1 example should work on EVK  A2 revision ?   I have read community and see this example might corrupt FPR and I have changed erase/write address :   //destAdrss = pflas...
    Eugene Hiihtaja
    last modified by Eugene Hiihtaja
  • GINT中断失效问题

    GINT使用边沿方式“或”运算过程中有疑问,请解答一下,谢谢。 GINT初始化2个以上引脚为同一组中断,图上举例为2个引脚为一组,且经过实测现象绘制。 当同组中无任一极性有效的信号时,任意一个引脚产生极性有效信号,则产生中断,这个可以理解; 当同组中有任一极性有效的信号时,任意一个引脚产生极性有效信号,也不产生中断,这个我无法理解。   当运用到实际当中时,我可能会在图上虚线指示位置进入P...
    Zhihong Li
    last modified by Zhihong Li
  • Flash programming granularity LPC55

    If I understand the UM correctly, using the FLASH peripheral flash can be read at a granularity of 16 bytes ("physical word"), and erased, written and programmed at a granularity of 512 bytes (1 page, 32 physical word...
    Nicolas Stalder
    last modified by Nicolas Stalder
  • LPC55S69 : secure MPU

    Hello !   I have active nonsecure MPU ( freeRTOS running on nonsecure side). But on secure side MPU is not used and not even disabled explicitly. Should I leave it untouched at all OR better to activate it wit...
    Eugene Hiihtaja
    created by Eugene Hiihtaja
  • Important updates when using LPCXpresso55S69 Revision A2 boards and 1B silicon

    The LPC55S6x family was initial silicon die version was 0A, and this silicon was using on Revision A1 LPCXpresso55S69 boards. Revision 1B silicon has been used on Revision A2 boards. Both versions of silicon support t...
    Brendon Slade
    last modified by Brendon Slade
  • LPC55S69: Flash driver init ,12Mhz vs 96 Mhz

    Hi ! Flash driver initialization require clock as part of init structure ( see fsl_iap.c )   status_t FLASH_Init(flash_config_t *config) { assert(VERSION1_FLASH_API_TREE); config->modeConfig.sysFreqInMHz =...
    Eugene Hiihtaja
    last modified by Eugene Hiihtaja
  • LPC55S69 : privileged or not ?

    Hello !   I have FreeRTOS on nonsecure side and tasks' with user privileges is running there. Task with user privileges call NSC function and on Secure side I have analyze CONTROL register:   int inPrivil...
    Eugene Hiihtaja
    created by Eugene Hiihtaja
  • LPC55s69 : Faulthandler in PowerDown mode

    Hello !   in UM is recommended to keep FaultHandler in SRAM when MCU in PowerDown mode. Do you have code example how do it ?   Regards, Eugene
    Eugene Hiihtaja
    last modified by Eugene Hiihtaja
  • dual bootloader of lpc55s69

    When I was executing LPC55S69' dual bootloader work,I have some questions here. 1/When I executed the program again with the AN12327 revision, I deliberately added a printf statement,However, the version number did no...
    小白 张
    last modified by 小白 张