• In FS6500 SBC, need to close S1 switch while releasing FSxB pins?

    The S1 switch between VPU_FS pin & Vpre shall be closed under which circumstances while releasing FSxB pins? As seen in the diagram of FS1B activation, switch S1 when closed, connects the Vpre & VPU_FS.  ...
    Vaibhav Sharma
    last modified by Vaibhav Sharma
  • TJA1145 under voltage detection time and INH disable time

    I have two questions on TJA1145. 1.In TJA1145 Under voltage detection time 54µs(mentioned on Datasheet) and under voltage detection to sleep mode time 200mS(as mentioned on datasheet), What will happen if TJA11...
    Michael brijith
    last modified by Michael brijith
  • Unable to generate interrupt from SBC!

    Hi,   SBC- FS6513C: How to generate a test case to check the working of interrupt? I've tried to reduce the power supply down to 2V which should fulfill the 1st category depicted below.   Have tried other ...
    Vaibhav Sharma
    last modified by Vaibhav Sharma
  • In the S32K14x example package,which example tells the operation of the SBC chip UJA113x_SER?

    Dear professor,       I want to know that how the MCU reads or writes a register in the SBC chip UJA113x_SER by SPI. I have tried to operate according to the datasheet but failed,so...
    cao chuang
    last modified by cao chuang
  • Visit us next week at NXP Connects 2019 Silcon Valley, June 12-13 in Santa Clara

    NXP Connects 2019 Silicon Valley   Visit us next week at NXP Connects 2019 Silcon Valley, June 12-13 in Santa Clara   We will run three sessions dedicated to our Safety PMIC solutions : Wednesday 3PM : ...
  • In FS6513, FLT_ERR_2:0 is showing Max value(6) at Init

    The FLT_ERR_2:0 bits is showing 6(FEC is configured for threshold 6) at the start of the SBC_Init function(before any of the other command being sent). So presently after initializing SPI & port drivers, SBC is be...
    Vaibhav Sharma
    last modified by Vaibhav Sharma
  • BAT_FAIL bit is always 0(Wakeup from LPOFF)

    BAT_FAIL bit in INIT_VREG register is always 0(Even on reset), which shows that the POR never occurred. I am using debug mode. The RSTB_EXT bit in DIAG_SF_IOs register is 1 every time, I run the code.   Q1. Why ...
    Vaibhav Sharma
    last modified by Vaibhav Sharma
  • In FS6500 SBC, what happens if MCU fails to service watchdog in the 1st 256ms refresh period?

    As to switch from INIT_FS mode to Normal_WD mode in SBC, 1 good watchdog refresh is essential by MCU; but if the MCU fails to do so in 256msec, then RSTB, FS0B & FS1B(after Tdelay time) are asserted low. So at thi...
    Vaibhav Sharma
    last modified by Vaibhav Sharma
  • NXP TECH-ACADEMY (Access Problem)

    Hi Team NXP ,   I was able to access NXP Technical Academy ( NXP Technical Academy ) till last Wednesday (06/MAR/2019).  ISSUE: But, since last Friday (08/MAR/2019), I am unable to access (A...
    Lakshmi Kanth
    last modified by Lakshmi Kanth
  • Three Generations of Safety Power Management ICs

    NXP's scalable safety power management portfolio combines safety features with device flexibility built on two pillars: safety process during the development phase and proven ASIL D safety architectures...
    Vincent Lagardelle
    last modified by Vincent Lagardelle
  • How To Apply UJA1075ATW Watchdog?

    HELLO According To Datasheet And Following Diagram Of UJA1075ATW Here Is Not WDI (Watchdog Input) To Be Periodically Kicked. So We're Confused About The Mechanism Of Watchdog Timer. In Our Case We Want To Apply Watch...
    Bright Wang
    last modified by Bright Wang